From 7493567982b0786069bf5a0754c96e940ae4978c Mon Sep 17 00:00:00 2001 From: Qingwei Hu Date: Sun, 20 Sep 2026 03:18:24 -0400 Subject: [PATCH] riscv: Add Zic64b to cpufeature and hwprobe Zic64b mandates 64-byte naturally aligned cache blocks and is a mandatory extension of the RVA22 and RVA23 profiles. Allocate a RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a validate callback that requires each cbom/cbop/cboz cache block size to be 64 bytes when it is present, and export it through hwprobe. Link: https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059 Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Signed-off-by: Qingwei Hu Co-developed-by: Guodong Xu Signed-off-by: Guodong Xu Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-4-5f14bc5c23d3@oss.qualcomm.com [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/cpufeature.c | 19 +++++++++++++++++++ arch/riscv/kernel/sys_hwprobe.c | 1 + 5 files changed, 26 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 69a3fc0a29b7..8454a6ae6fd1 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -427,3 +427,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_B`: The B extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions, and implies the presence of the Zba, Zbb, and Zbs sub-extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZIC64B`: The Zic64b extension is supported, + as defined in the RISC-V Profiles specification starting from commit + b1d80660 ("Updated to ratified state.") diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6a693210b251..b103aaeafa47 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -123,6 +123,7 @@ #define RISCV_ISA_EXT_ZICCAMOA 113 #define RISCV_ISA_EXT_ZICCIF 114 #define RISCV_ISA_EXT_ZA64RS 115 +#define RISCV_ISA_EXT_ZIC64B 116 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9323feb7c3c8..9a121ee3b436 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -123,6 +123,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZICCRSE _BITULL(4) #define RISCV_HWPROBE_EXT_ZA64RS _BITULL(5) #define RISCV_HWPROBE_EXT_B _BITULL(6) +#define RISCV_HWPROBE_EXT_ZIC64B _BITULL(7) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6d5d2eecb85c..1aead2399c2e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -136,6 +136,24 @@ static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data, return 0; } +static int riscv_ext_zic64b_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + /* + * Zic64b mandates 64-byte naturally aligned cache blocks; cross-check the + * cbom/cbop/cboz block-size (when declared) device-tree properties to + * avoid inconsistency. + */ + if ((riscv_cbom_block_size && riscv_cbom_block_size != 64) || + (riscv_cbop_block_size && riscv_cbop_block_size != 64) || + (riscv_cboz_block_size && riscv_cboz_block_size != 64)) { + pr_err("Zic64b detected in ISA string, disabling as a CBO block size is not 64 bytes\n"); + return -EINVAL; + } + + return 0; +} + static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -542,6 +560,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv_ext_vector_float_validate), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H), + __RISCV_ISA_EXT_DATA_VALIDATE(zic64b, RISCV_ISA_EXT_ZIC64B, riscv_ext_zic64b_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index c03c6e08dd4d..8a38a4d37806 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -208,6 +208,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing); EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing); EXT_KEY(isainfo->isa, B, pair->value, missing); + EXT_KEY(isainfo->isa, ZIC64B, pair->value, missing); } /* Now turn off reporting features if any CPU is missing it. */