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net: dsa: lantiq_gswip: replace *_mask() functions with regmap API
Use coccinelle to replace all uses of *_mask() with an equivalent call to regmap_write_bits(). // Replace gswip_switch_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_switch_mask(priv, clear, set, offset) + regmap_write_bits(priv->gswip, offset, clear | set, set) // Replace gswip_mdio_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_mdio_mask(priv, clear, set, offset) + regmap_write_bits(priv->mdio, offset, clear | set, set) // Replace gswip_mii_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_mii_mask(priv, clear, set, offset) + regmap_write_bits(priv->mii, offset, clear | set, set) Remove the new unused *_mask() functions. This naive approach will be further optmized manually in the next commit. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Acked-by; Hauke Mehrtens <hauke@hauke-m.de>: Acked-by; Hauke Mehrtens <hauke@hauke-m.de>: Link: https://patch.msgid.link/258d931386a512b7089924c70073ca7acba71168.1761045000.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle
Jakub Kicinski
parent
4cc06901ef
commit
748b0aebd4
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@ -111,12 +111,6 @@ static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = {
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MIB_DESC(2, 0x0E, "TxGoodBytes"),
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};
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static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,
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u32 offset)
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{
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regmap_write_bits(priv->gswip, offset, clear | set, set);
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}
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static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
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u32 cleared)
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{
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@ -126,18 +120,6 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,
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!(val & cleared), 20, 50000);
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}
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static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,
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u32 offset)
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{
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regmap_write_bits(priv->mdio, offset, clear | set, set);
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}
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static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
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u32 offset)
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{
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regmap_write_bits(priv->mii, offset, clear | set, set);
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}
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static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
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int port)
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{
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@ -149,7 +131,8 @@ static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
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reg_port = port + priv->hw_info->mii_port_reg_offset;
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gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port));
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regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), clear | set,
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set);
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}
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static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
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@ -165,13 +148,16 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
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switch (reg_port) {
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case 0:
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gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
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regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, clear | set,
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set);
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break;
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case 1:
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gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);
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regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, clear | set,
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set);
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break;
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case 5:
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gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);
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regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, clear | set,
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set);
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break;
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}
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}
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@ -287,10 +273,11 @@ static int gswip_pce_table_entry_read(struct gswip_priv *priv,
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goto out_unlock;
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regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
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gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
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regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
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GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
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tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,
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GSWIP_PCE_TBL_CTRL);
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tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS);
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err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,
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GSWIP_PCE_TBL_CTRL_BAS);
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@ -348,10 +335,11 @@ static int gswip_pce_table_entry_write(struct gswip_priv *priv,
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}
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regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);
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gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
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regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
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GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
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tbl->table | addr_mode,
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GSWIP_PCE_TBL_CTRL);
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tbl->table | addr_mode);
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for (i = 0; i < ARRAY_SIZE(tbl->key); i++)
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regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]);
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@ -359,10 +347,11 @@ static int gswip_pce_table_entry_write(struct gswip_priv *priv,
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for (i = 0; i < ARRAY_SIZE(tbl->val); i++)
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regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]);
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gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
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regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
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GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
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tbl->table | addr_mode,
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GSWIP_PCE_TBL_CTRL);
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tbl->table | addr_mode);
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regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask);
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@ -449,8 +438,9 @@ static int gswip_port_enable(struct dsa_switch *ds, int port,
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if (phydev)
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mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
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GSWIP_MDIO_PHY_ADDR_MASK | mdio_phy,
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mdio_phy);
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}
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/* RMON Counter Enable for port */
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@ -480,9 +470,11 @@ static int gswip_pce_load_microcode(struct gswip_priv *priv)
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int i;
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int err;
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gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK,
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GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
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regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,
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GSWIP_PCE_TBL_CTRL_ADDR_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_MASK |
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GSWIP_PCE_TBL_CTRL_OPMOD_ADWR,
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GSWIP_PCE_TBL_CTRL_OPMOD_ADWR);
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regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0);
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for (i = 0; i < priv->hw_info->pce_microcode_size; i++) {
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@ -549,9 +541,10 @@ static void gswip_port_commit_pvid(struct gswip_priv *priv, int port)
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}
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vinr = idx ? GSWIP_PCE_VCTRL_VINR_ALL : GSWIP_PCE_VCTRL_VINR_TAGGED;
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gswip_switch_mask(priv, GSWIP_PCE_VCTRL_VINR,
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regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
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GSWIP_PCE_VCTRL_VINR |
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FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr),
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GSWIP_PCE_VCTRL(port));
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FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr));
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/* Note that in GSWIP 2.2 VLAN mode the VID needs to be programmed
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* directly instead of referencing the index in the Active VLAN Tablet.
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@ -569,20 +562,27 @@ static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
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if (vlan_filtering) {
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/* Use tag based VLAN */
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gswip_switch_mask(priv,
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GSWIP_PCE_VCTRL_VSR,
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GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
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GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0,
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GSWIP_PCE_VCTRL(port));
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regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
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GSWIP_PCE_VCTRL_VSR |
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GSWIP_PCE_VCTRL_UVR |
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GSWIP_PCE_VCTRL_VIMR |
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GSWIP_PCE_VCTRL_VEMR |
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GSWIP_PCE_VCTRL_VID0,
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GSWIP_PCE_VCTRL_UVR |
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GSWIP_PCE_VCTRL_VIMR |
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GSWIP_PCE_VCTRL_VEMR |
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GSWIP_PCE_VCTRL_VID0);
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regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
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GSWIP_PCE_PCTRL_0_TVM);
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} else {
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/* Use port based VLAN */
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gswip_switch_mask(priv,
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GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
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GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0,
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regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),
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GSWIP_PCE_VCTRL_UVR |
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GSWIP_PCE_VCTRL_VIMR |
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GSWIP_PCE_VCTRL_VEMR |
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GSWIP_PCE_VCTRL_VID0 |
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GSWIP_PCE_VCTRL_VSR,
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GSWIP_PCE_VCTRL(port));
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GSWIP_PCE_VCTRL_VSR);
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regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
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GSWIP_PCE_PCTRL_0_TVM);
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}
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@ -642,7 +642,7 @@ static int gswip_setup(struct dsa_switch *ds)
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regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0);
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/* Configure the MDIO Clock 2.5 MHz */
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gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
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regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff | 0x09, 0x09);
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/* bring up the mdio bus */
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err = gswip_mdio(priv);
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@ -1083,8 +1083,9 @@ static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
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regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),
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GSWIP_SDMA_PCTRL_EN);
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gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,
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GSWIP_PCE_PCTRL_0p(port));
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regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),
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GSWIP_PCE_PCTRL_0_PSTATE_MASK | stp_state,
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stp_state);
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}
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static int gswip_port_fdb(struct dsa_switch *ds, int port,
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@ -1313,8 +1314,8 @@ static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
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else
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mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
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GSWIP_MDIO_PHY_LINK_MASK | mdio_phy, mdio_phy);
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}
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static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
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@ -1354,11 +1355,11 @@ static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
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break;
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}
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
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GSWIP_MDIO_PHY_SPEED_MASK | mdio_phy, mdio_phy);
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gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,
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GSWIP_MAC_CTRL_0p(port));
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regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
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GSWIP_MAC_CTRL_0_GMII_MASK | mac_ctrl_0, mac_ctrl_0);
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}
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static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
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@ -1373,10 +1374,10 @@ static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
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mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;
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}
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,
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GSWIP_MAC_CTRL_0p(port));
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gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,
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GSWIP_MDIO_PHYp(port));
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regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
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GSWIP_MAC_CTRL_0_FDUP_MASK | mac_ctrl_0, mac_ctrl_0);
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regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
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GSWIP_MDIO_PHY_FDUP_MASK | mdio_phy, mdio_phy);
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}
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static void gswip_port_set_pause(struct gswip_priv *priv, int port,
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@ -1402,12 +1403,11 @@ static void gswip_port_set_pause(struct gswip_priv *priv, int port,
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GSWIP_MDIO_PHY_FCONRX_DIS;
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}
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gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,
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mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));
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gswip_mdio_mask(priv,
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GSWIP_MDIO_PHY_FCONTX_MASK |
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GSWIP_MDIO_PHY_FCONRX_MASK,
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mdio_phy, GSWIP_MDIO_PHYp(port));
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regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),
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GSWIP_MAC_CTRL_0_FCON_MASK | mac_ctrl_0, mac_ctrl_0);
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regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),
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GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK | mdio_phy,
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mdio_phy);
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}
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static void gswip_phylink_mac_config(struct phylink_config *config,
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@ -1526,10 +1526,10 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
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int err;
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regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index);
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gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |
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GSWIP_BM_RAM_CTRL_OPMOD,
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table | GSWIP_BM_RAM_CTRL_BAS,
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GSWIP_BM_RAM_CTRL);
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regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL,
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GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD |
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table | GSWIP_BM_RAM_CTRL_BAS,
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table | GSWIP_BM_RAM_CTRL_BAS);
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err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
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GSWIP_BM_RAM_CTRL_BAS);
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