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mmc: sdhci-msm: convert to use custom crypto profile
As is being done in ufs-qcom, make the sdhci-msm driver override the full crypto profile rather than "just" key programming and eviction. This makes it much more straightforward to add support for hardware-wrapped inline encryption keys. It also makes it easy to pass the original blk_crypto_key down to qcom_ice_program_key() once it is updated to require the key in that form. Signed-off-by: Eric Biggers <ebiggers@google.com> Message-ID: <20241213041958.202565-8-ebiggers@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Eric Biggers
Ulf Hansson
parent
08a7ead324
commit
741521fa27
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@ -28,16 +28,13 @@ cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile)
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return mmc_from_crypto_profile(profile)->cqe_private;
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}
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static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg,
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int slot)
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static void cqhci_crypto_program_key(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg,
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int slot)
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{
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u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
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int i;
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if (cq_host->ops->program_key)
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return cq_host->ops->program_key(cq_host, cfg, slot);
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/* Clear CFGE */
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cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
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@ -52,7 +49,6 @@ static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
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/* Write dword 16, which includes the new value of CFGE */
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cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
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slot_offset + 16 * sizeof(cfg->reg_val[0]));
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return 0;
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}
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static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
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@ -69,7 +65,6 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
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int i;
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int cap_idx = -1;
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union cqhci_crypto_cfg_entry cfg = {};
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int err;
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BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
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for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
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@ -96,10 +91,10 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
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memcpy(cfg.crypto_key, key->raw, key->size);
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}
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err = cqhci_crypto_program_key(cq_host, &cfg, slot);
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cqhci_crypto_program_key(cq_host, &cfg, slot);
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memzero_explicit(&cfg, sizeof(cfg));
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return err;
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return 0;
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}
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static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
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@ -110,7 +105,8 @@ static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
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*/
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union cqhci_crypto_cfg_entry cfg = {};
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return cqhci_crypto_program_key(cq_host, &cfg, slot);
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cqhci_crypto_program_key(cq_host, &cfg, slot);
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return 0;
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}
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static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile,
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@ -167,7 +163,6 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
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struct mmc_host *mmc = cq_host->mmc;
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struct device *dev = mmc_dev(mmc);
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struct blk_crypto_profile *profile = &mmc->crypto_profile;
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unsigned int num_keyslots;
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unsigned int cap_idx;
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enum blk_crypto_mode_num blk_mode_num;
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unsigned int slot;
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@ -177,6 +172,9 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
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!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
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goto out;
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if (cq_host->ops->uses_custom_crypto_profile)
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goto profile_initialized;
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cq_host->crypto_capabilities.reg_val =
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cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
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@ -195,9 +193,8 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
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* CCAP.CFGC is off by one, so the actual number of crypto
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* configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
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*/
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num_keyslots = cq_host->crypto_capabilities.config_count + 1;
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err = devm_blk_crypto_profile_init(dev, profile, num_keyslots);
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err = devm_blk_crypto_profile_init(
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dev, profile, cq_host->crypto_capabilities.config_count + 1);
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if (err)
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goto out;
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@ -225,9 +222,11 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
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cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
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}
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profile_initialized:
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/* Clear all the keyslots so that we start in a known state. */
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for (slot = 0; slot < num_keyslots; slot++)
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cqhci_crypto_clear_keyslot(cq_host, slot);
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for (slot = 0; slot < profile->num_slots; slot++)
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profile->ll_ops.keyslot_evict(profile, NULL, slot);
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/* CQHCI crypto requires the use of 128-bit task descriptors. */
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cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
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@ -289,13 +289,11 @@ struct cqhci_host_ops {
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u64 *data);
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void (*pre_enable)(struct mmc_host *mmc);
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void (*post_disable)(struct mmc_host *mmc);
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#ifdef CONFIG_MMC_CRYPTO
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int (*program_key)(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg, int slot);
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#endif
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void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc,
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dma_addr_t addr, int len, bool end, bool dma64);
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#ifdef CONFIG_MMC_CRYPTO
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bool uses_custom_crypto_profile;
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#endif
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};
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static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
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@ -1807,12 +1807,19 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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#ifdef CONFIG_MMC_CRYPTO
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static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
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static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
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struct cqhci_host *cq_host)
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{
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struct mmc_host *mmc = msm_host->mmc;
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struct blk_crypto_profile *profile = &mmc->crypto_profile;
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struct device *dev = mmc_dev(mmc);
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struct qcom_ice *ice;
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union cqhci_crypto_capabilities caps;
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union cqhci_crypto_cap_entry cap;
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int err;
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int i;
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if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
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return 0;
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@ -1827,8 +1834,37 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
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return PTR_ERR_OR_ZERO(ice);
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msm_host->ice = ice;
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mmc->caps2 |= MMC_CAP2_CRYPTO;
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/* Initialize the blk_crypto_profile */
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caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
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/* The number of keyslots supported is (CFGC+1) */
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err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
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if (err)
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return err;
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profile->ll_ops = sdhci_msm_crypto_ops;
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profile->max_dun_bytes_supported = 4;
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profile->dev = dev;
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/*
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* Currently this driver only supports AES-256-XTS. All known versions
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* of ICE support it, but to be safe make sure it is really declared in
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* the crypto capability registers. The crypto capability registers
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* also give the supported data unit size(s).
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*/
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for (i = 0; i < caps.num_crypto_cap; i++) {
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cap.reg_val = cpu_to_le32(cqhci_readl(cq_host,
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CQHCI_CRYPTOCAP +
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i * sizeof(__le32)));
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if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS &&
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cap.key_size == CQHCI_CRYPTO_KEY_SIZE_256)
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profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
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cap.sdus_mask * 512;
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}
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mmc->caps2 |= MMC_CAP2_CRYPTO;
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return 0;
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}
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@ -1854,35 +1890,55 @@ static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
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return 0;
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}
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/*
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* Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
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* vendor-specific SCM calls for this; it doesn't support the standard way.
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*/
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static int sdhci_msm_program_key(struct cqhci_host *cq_host,
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const union cqhci_crypto_cfg_entry *cfg,
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int slot)
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static inline struct sdhci_msm_host *
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sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
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{
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struct sdhci_host *host = mmc_priv(cq_host->mmc);
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struct mmc_host *mmc = mmc_from_crypto_profile(profile);
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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union cqhci_crypto_cap_entry cap;
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if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
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return qcom_ice_evict_key(msm_host->ice, slot);
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return msm_host;
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}
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/*
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* Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
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* for this; it doesn't support the standard way.
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*/
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static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct sdhci_msm_host *msm_host =
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sdhci_msm_host_from_crypto_profile(profile);
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/* Only AES-256-XTS has been tested so far. */
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cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
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if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
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cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
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return -EINVAL;
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if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS)
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return -EOPNOTSUPP;
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return qcom_ice_program_key(msm_host->ice,
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QCOM_ICE_CRYPTO_ALG_AES_XTS,
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QCOM_ICE_CRYPTO_KEY_SIZE_256,
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cfg->crypto_key,
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cfg->data_unit_size, slot);
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key->raw,
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key->crypto_cfg.data_unit_size / 512,
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slot);
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}
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static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile,
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const struct blk_crypto_key *key,
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unsigned int slot)
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{
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struct sdhci_msm_host *msm_host =
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sdhci_msm_host_from_crypto_profile(profile);
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return qcom_ice_evict_key(msm_host->ice, slot);
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}
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static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = {
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.keyslot_program = sdhci_msm_ice_keyslot_program,
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.keyslot_evict = sdhci_msm_ice_keyslot_evict,
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};
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#else /* CONFIG_MMC_CRYPTO */
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static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
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@ -1988,7 +2044,7 @@ static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
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.enable = sdhci_msm_cqe_enable,
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.disable = sdhci_msm_cqe_disable,
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#ifdef CONFIG_MMC_CRYPTO
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.program_key = sdhci_msm_program_key,
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.uses_custom_crypto_profile = true,
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#endif
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};
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