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dt-bindings: PCI: amlogic,axg-pcie: Fix select schema
The amlogic,axg-pcie binding was never enabled as the 'select' schema expects a single compatible value, but the binding has a fallback compatible. Fix the 'select' by adding a 'contains'. With this, several errors in the clock and reset properties are exposed. Some of the names aren't defined in the common DWC schema and the order of clocks entries doesn't match .dts files. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251024011122.26001-1-robh@kernel.org
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@ -20,9 +20,10 @@ allOf:
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select:
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properties:
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compatible:
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enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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contains:
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enum:
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- amlogic,axg-pcie
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- amlogic,g12a-pcie
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required:
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- compatible
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@ -51,15 +52,15 @@ properties:
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clocks:
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items:
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- description: PCIe PHY clock
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- description: PCIe GEN 100M PLL clock
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- description: PCIe RC clock gate
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- description: PCIe PHY clock
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clock-names:
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items:
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- const: general
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- const: pclk
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- const: port
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- const: general
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phys:
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maxItems: 1
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@ -88,7 +89,7 @@ required:
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- reg
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- reg-names
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- interrupts
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- clock
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- clocks
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- clock-names
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- "#address-cells"
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- "#size-cells"
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@ -115,8 +116,8 @@ examples:
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reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
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reg-names = "elbi", "cfg", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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clocks = <&pclk>, <&clk_port>, <&clk_phy>;
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clock-names = "pclk", "port", "general";
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clocks = <&clk_phy>, <&pclk>, <&clk_port>;
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clock-names = "general", "pclk", "port";
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resets = <&reset_pcie_port>, <&reset_pcie_apb>;
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reset-names = "port", "apb";
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phys = <&pcie_phy>;
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@ -115,11 +115,11 @@ properties:
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above for new bindings.
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oneOf:
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- description: See native 'dbi' clock for details
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enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]
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enum: [ pcie, pcie_apb_sys, aclk_dbi, reg, port ]
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- description: See native 'mstr/slv' clock for details
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enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
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- description: See native 'pipe' clock for details
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enum: [ pcie_phy, pcie_phy_ref, link ]
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enum: [ pcie_phy, pcie_phy_ref, link, general ]
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- description: See native 'aux' clock for details
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enum: [ pcie_aux ]
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- description: See native 'ref' clock for details.
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@ -176,7 +176,7 @@ properties:
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- description: See native 'phy' reset for details
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enum: [ pciephy, link ]
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- description: See native 'pwr' reset for details
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enum: [ turnoff ]
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enum: [ turnoff, port ]
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phys:
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description:
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