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drm/xe/pvc: Force even num engines to use 64B

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Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Niranjana Vishwanathapura 2023-07-18 10:45:28 +00:00 committed by Rodrigo Vivi
parent 25063811d9
commit 7407f2e5c3
2 changed files with 11 additions and 0 deletions
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1
drivers/gpu/drm/xe/regs/xe_engine_regs.h
View File

@ -64,6 +64,7 @@
#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
#define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
#define BCS_SWCTRL_DISABLE_256B REG_BIT(2)
/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
#define BLIT_CCTL(base) XE_REG((base) + 0x204)

10
drivers/gpu/drm/xe/xe_wa.c
View File

@ -604,6 +604,16 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
},
/* PVC */
{ XE_RTP_NAME("16017236439"),
XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
FUNC(xe_rtp_match_even_instance)),
XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
BCS_SWCTRL_DISABLE_256B,
XE_RTP_ACTION_FLAG(ENGINE_BASE))),
},
/* Xe_LPG */
{ XE_RTP_NAME("18019271663"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),