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arm64: dts: qcom: sm8750: enable ETR and CTCU devices

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Embedded Trace Router(ETR) is working as a DDR memory sink to collect
tracing data from source device and the CTCU device serves as the
control unit for the ETR device.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jie Gan 2026-02-04 10:22:03 +08:00 committed by Bjorn Andersson
parent 8017f8fa34
commit 73d469b4f5
1 changed files with 177 additions and 0 deletions
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177
arch/arm64/boot/dts/qcom/sm8750.dtsi
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@ -4141,6 +4141,35 @@ tcsrcc: clock-controller@f204008 {
#reset-cells = <1>;
};
ctcu@10001000 {
compatible = "qcom,sm8750-ctcu", "qcom,sa8775p-ctcu";
reg = <0x0 0x10001000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ctcu_in0: endpoint {
remote-endpoint = <&etr0_out>;
};
};
port@1 {
reg = <1>;
ctcu_in1: endpoint {
remote-endpoint = <&etr1_out>;
};
};
};
};
stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
@ -4255,6 +4284,122 @@ funnel_in0_out: endpoint {
};
};
replicator@10046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10046000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
qdss_rep_in: endpoint {
remote-endpoint = <&swao_rep_out0>;
};
};
};
out-ports {
port {
qdss_rep_out0: endpoint {
remote-endpoint = <&etr_rep_in>;
};
};
};
};
tmc@10048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10048000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x04e0 0x0>;
arm,scatter-gather;
in-ports {
port {
etr0_in: endpoint {
remote-endpoint = <&etr_rep_out0>;
};
};
};
out-ports {
port {
etr0_out: endpoint {
remote-endpoint = <&ctcu_in0>;
};
};
};
};
replicator@1004e000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x1004e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
etr_rep_in: endpoint {
remote-endpoint = <&qdss_rep_out0>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etr_rep_out0: endpoint {
remote-endpoint = <&etr0_in>;
};
};
port@1 {
reg = <1>;
etr_rep_out1: endpoint {
remote-endpoint = <&etr1_in>;
};
};
};
};
tmc_etr1: tmc@1004f000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x1004f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
iommus = <&apps_smmu 0x0500 0x0>;
arm,scatter-gather;
arm,buffer-size = <0x400000>;
in-ports {
port {
etr1_in: endpoint {
remote-endpoint = <&etr_rep_out1>;
};
};
};
out-ports {
port {
etr1_out: endpoint {
remote-endpoint = <&ctcu_in1>;
};
};
};
};
tpdm@10800000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10800000 0x0 0x1000>;
@ -4943,6 +5088,38 @@ tmc_etf_in: endpoint {
};
};
};
out-ports {
port {
tmc_etf_out: endpoint {
remote-endpoint = <&swao_rep_in>;
};
};
};
};
replicator@10b06000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x10b06000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
swao_rep_in: endpoint {
remote-endpoint = <&tmc_etf_out>;
};
};
};
out-ports {
port {
swao_rep_out0: endpoint {
remote-endpoint = <&qdss_rep_in>;
};
};
};
};
tpda@10b08000 {