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drm/msm: Reject MAP_NULL op if no PRR

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We need PRR support in order to implement MAP_NULL.  Userspace shouldn't
be trying to use this if it is unsupported.

Reported-by: Valentine Burley <valentine.burley@collabora.com>
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37935#note_3153730
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Tested-by: Valentine Burley <valentine.burley@collabora.com>
Patchwork: https://patchwork.freedesktop.org/patch/682941/
Message-ID: <20251022222051.10030-1-robin.clark@oss.qualcomm.com>
This commit is contained in:
Rob Clark 2025-10-22 15:20:51 -07:00
parent 7f9335f2d9
commit 73b7e48a87
3 changed files with 17 additions and 7 deletions
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7
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -348,13 +348,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
return 0;
}
static bool
adreno_smmu_has_prr(struct msm_gpu *gpu)
{
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
return adreno_smmu && adreno_smmu->set_prr_addr;
}
int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
uint32_t param, uint64_t *value, uint32_t *len)
{

6
drivers/gpu/drm/msm/msm_gem_vma.c
View File

@ -964,6 +964,7 @@ static int
lookup_op(struct msm_vm_bind_job *job, const struct drm_msm_vm_bind_op *op)
{
struct drm_device *dev = job->vm->drm;
struct msm_drm_private *priv = dev->dev_private;
int i = job->nr_ops++;
int ret = 0;
@ -1010,6 +1011,11 @@ lookup_op(struct msm_vm_bind_job *job, const struct drm_msm_vm_bind_op *op)
break;
}
if ((op->op == MSM_VM_BIND_OP_MAP_NULL) &&
!adreno_smmu_has_prr(priv->gpu)) {
ret = UERR(EINVAL, dev, "PRR not supported\n");
}
return ret;
}

11
drivers/gpu/drm/msm/msm_gpu.h
View File

@ -299,6 +299,17 @@ static inline struct msm_gpu *dev_to_gpu(struct device *dev)
return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
}
static inline bool
adreno_smmu_has_prr(struct msm_gpu *gpu)
{
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
if (!adreno_smmu)
return false;
return adreno_smmu && adreno_smmu->set_prr_addr;
}
/* It turns out that all targets use the same ringbuffer size */
#define MSM_GPU_RINGBUFFER_SZ SZ_32K
#define MSM_GPU_RINGBUFFER_BLKSIZE 32