mirror of
https://github.com/torvalds/linux.git
synced 2026-05-28 09:04:39 +02:00
Samsung DTS ARM64 changes for v6.14
1. Exynos8895: Add UART nodes, PMU (performance) for the M2 cluster and
I2C controllers in the camera block (HSI2C in CAM0-3).
2. Exynos990: Add Power Management Unit (Samsung block), PMU
(performance) for M5 cluster and two clock controllers.
3. ExynosAutov920: Add watchdog and DMA controllers.
4. Google GS101: Minor fixes for phy and USB. Add USB Type-C.
5. Exynos850-e850-96 board: Drop gap in memory layout.
6. New SoC: Exynos9810.
7. New boards, all mobile phones:
- Exynos9810:
Samsung Galaxy S9 (SM-G960F)
- Exynos990:
Samsung Galaxy S20 FE (SM-G780F)
Samsung Galaxy S20 5G (SM-G980F)
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmdz7fUQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD13DVD/wN2KLgyIb3xLzcWN6exT9AP+WzOXZteIqE
YZzRIbc/trQlwPCh3RKTFjP4Oqo4lRv6oC+zEo1L/foLRhP2f4YOp6hspQdjmxvt
GGk98GIHLGvIColtk/drPUOkl0C/xaoKJXV6EzYBM3x8dEBGn0RqDAdN3fiOBEMU
xgbPr9+T5lJxpm1ZR3PQUqlySq48M4B2kptd2QJzprujyREAKLKPL3Zy02mPCWGA
zgUkoP1bnPp5HR78zZtF4u0eJsHWx/GOUq+y0q6xA9lZ3QOL5wvL/uyJvJVIDO3D
yGHjfrZYME1vFVlF6HLg3St0ISFspZiZV1ToWIlbBln+uIGrden24An1aR+svbtw
+v7MM617PYB8356wHEweIg0+rDrhnqokefn20L6z7QEr/4SfFOzjhrcKQUCcjL2c
cejfvL1jN/2kzP0ia5A0Y5wS/NVHwporFsI03+RQVXBqowzVTJueIGmPt7BHcvgC
y3xp0jE/C22JPVSKbR4SsNCiSjM9Q2NqomjS385vZPhDwCFgMKobZ1QhZ1ef3gN9
rL1lpbxe4mhJP4iCFW7p3Tl0x7UL/5Oo874t4iHEsU4NjaKrw2hE/0vXrNn/dRE9
SO8jK/ZG1zMo8npvKKSw+Qa9oX4mM5uhkZa4VkeSVtM5QPyHmO/Xyb+8fpSh/7/R
KRbzIKIbSw==
=Ps/u
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmeH9ZEACgkQYKtH/8kJ
UiftNxAAr1VHsS7oW4h2viFwGnVK4g6cx0TIPrIar5XoxrmBiv3McZyLsFFpzaLE
Cbb4W0ikWriCAHrs6GQhFlEhLv/isveBvjZIRO1Y5rClUPLXkdHNYuWMhwCFeofc
9uW6Ti/uXCAAkgt8h+qdaglXiOedNTAmqq+iHBMnD9JeMm42wcMdUx2ZUcGiOPe7
PkdFVA2e8d0crVrXLwgwOaBcsx93xKSJDy8VWIejn5wOCgVnVJR90v38O8itrXo8
W26ddAnlpKuSMq1Kj5iFnaj1A6ODswNuXKN7IgekfGprSE1ZtdG1CVmVPo/c5X7+
bELBxexSuCz/o9bieBeBLAzCFTgw1MqJDdXmoGIfqqHNALoFpaPMKHpDTnBpNgef
DfA3U5ai+QtI+AqtR0qhV6ltCJKFimx3PdBR0P+FegvswMitCwJScIoGje4xOR7A
VUYTyMRLES4GsC9m9K/442Vnk7LIRPfzOZXTUWbVfPd50BTc8rexjUEJLD8LwFfJ
0PDtDD5JRR1MK+cgzBKTJVSUBd4AyZmYRWlA1+fI9//Ir3NO9kZWlF0nUgLAWS5m
KS3Rdy4RVj2XPuszpsMVjCwShNNEeKT1WQnK6QM9eUvPp0m1y8oMWgtHwkn0gjD9
mt4cSREdbE8U/MhO/FhKlq0g4RdmOp6fEjfUVstzo2GvW5xo420=
=iQYo
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.14
1. Exynos8895: Add UART nodes, PMU (performance) for the M2 cluster and
I2C controllers in the camera block (HSI2C in CAM0-3).
2. Exynos990: Add Power Management Unit (Samsung block), PMU
(performance) for M5 cluster and two clock controllers.
3. ExynosAutov920: Add watchdog and DMA controllers.
4. Google GS101: Minor fixes for phy and USB. Add USB Type-C.
5. Exynos850-e850-96 board: Drop gap in memory layout.
6. New SoC: Exynos9810.
7. New boards, all mobile phones:
- Exynos9810:
Samsung Galaxy S9 (SM-G960F)
- Exynos990:
Samsung Galaxy S20 FE (SM-G780F)
Samsung Galaxy S20 5G (SM-G980F)
* tag 'samsung-dt64-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (23 commits)
arm64: dts: exynos8895: Add camera hsi2c nodes
arm64: dts: exynos990: Add clock management unit nodes
arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode
arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi
arm64: dts: exynos: Add initial support for Samsung Galaxy S9 (SM-G960F)
arm64: dts: exynos: Add Exynos9810 SoC support
arm64: dts: exynos850-e850-96: Specify reserved secure memory explicitly
arm64: dts: exynos990: Add a PMU node for the third cluster
arm64: dts: exynosautov920: Add DMA nodes
arm64: dts: exynos8895: Add a PMU node for the second cluster
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
arm64: dts: exynosautov920: add watchdog DT node
arm64: dts: exynos: Add initial support for Samsung Galaxy S20 (x1slte)
arm64: dts: exynos: Add initial support for Samsung Galaxy S20 5G (x1s)
arm64: dts: exynos: Add initial support for Samsung Galaxy S20 Series boards (x1s-common)
dt-bindings: arm: samsung: samsung-boards: Add bindings for SM-G981B and SM-G980F board
arm64: dts: exynos: gs101: allow stable USB phy Vbus detection
arm64: dts: exynos: gs101: phy region for exynos5-usbdrd is larger
MAINTAINERS: add myself and Tudor as reviewers for Google Tensor SoC
arm64: dts: exynos990: Add pmu and syscon-reboot nodes
...
Link: https://lore.kernel.org/r/20241231131742.134329-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
73a2e82123
|
|
@ -240,6 +240,9 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
|
||||
- samsung,r8s # Samsung Galaxy S20 FE (SM-G780F)
|
||||
- samsung,x1s # Samsung Galaxy S20 5G (SM-G981B)
|
||||
- samsung,x1slte # Samsung Galaxy S20 (SM-G980F)
|
||||
- const: samsung,exynos990
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
|
|
|
|||
|
|
@ -0,0 +1,121 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos990 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos990 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos990.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-top
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_HSI0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: usb31drd
|
||||
- const: usbdp_debug
|
||||
- const: dpgtc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos990.h>
|
||||
|
||||
cmu_hsi0: clock-controller@10a00000 {
|
||||
compatible = "samsung,exynos990-cmu-hsi0";
|
||||
reg = <0x10a00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
|
||||
clock-names = "oscclk",
|
||||
"bus",
|
||||
"usb31drd",
|
||||
"usbdp_debug",
|
||||
"dpgtc";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -9755,9 +9755,12 @@ F: drivers/firmware/google/
|
|||
|
||||
GOOGLE TENSOR SoC SUPPORT
|
||||
M: Peter Griffin <peter.griffin@linaro.org>
|
||||
R: André Draszik <andre.draszik@linaro.org>
|
||||
R: Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
C: irc://irc.oftc.net/pixel6-kernel-dev
|
||||
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
|
||||
F: arch/arm64/boot/dts/exynos/google/
|
||||
F: drivers/clk/samsung/clk-gs101.c
|
||||
|
|
|
|||
|
|
@ -8,6 +8,10 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
|
|||
exynos7885-jackpotlte.dtb \
|
||||
exynos850-e850-96.dtb \
|
||||
exynos8895-dreamlte.dtb \
|
||||
exynos9810-starlte.dtb \
|
||||
exynos990-c1s.dtb \
|
||||
exynos990-r8s.dtb \
|
||||
exynos990-x1s.dtb \
|
||||
exynos990-x1slte.dtb \
|
||||
exynosautov9-sadk.dtb \
|
||||
exynosautov920-sadk.dtb
|
||||
|
|
|
|||
|
|
@ -45,17 +45,9 @@ usb_dr_connector: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* RAM: 4 GiB (eMCP):
|
||||
* - 2 GiB at 0x80000000
|
||||
* - 2 GiB at 0x880000000
|
||||
*
|
||||
* 0xbab00000..0xbfffffff: secure memory (85 MiB).
|
||||
*/
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x3ab00000>,
|
||||
<0x0 0xc0000000 0x40000000>,
|
||||
reg = <0x0 0x80000000 0x80000000>,
|
||||
<0x8 0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
|
|
@ -146,6 +138,11 @@ reserved-memory {
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
secure_mem: memory@bab00000 {
|
||||
reg = <0x0 0xbab00000 0x5500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ramoops@f0000000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0x0 0xf0000000 0x200000>;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,17 @@ arm-a53-pmu {
|
|||
<&cpu3>;
|
||||
};
|
||||
|
||||
/* There's no PMU model for the Mongoose cores */
|
||||
mongoose-m2-pmu {
|
||||
compatible = "samsung,mongoose-pmu";
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu4>,
|
||||
<&cpu5>,
|
||||
<&cpu6>,
|
||||
<&cpu7>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -218,6 +228,19 @@ cmu_peric0: clock-controller@10400000 {
|
|||
"usi1", "usi2", "usi3";
|
||||
};
|
||||
|
||||
serial_0: serial@10430000 {
|
||||
compatible = "samsung,exynos8895-uart";
|
||||
reg = <0x10430000 0x100>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus>;
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@104d0000 {
|
||||
compatible = "samsung,exynos8895-pinctrl";
|
||||
reg = <0x104d0000 0x1000>;
|
||||
|
|
@ -250,12 +273,69 @@ cmu_peric1: clock-controller@10800000 {
|
|||
"usi10", "usi11", "usi12", "usi13";
|
||||
};
|
||||
|
||||
serial_1: serial@10830000 {
|
||||
compatible = "samsung,exynos8895-uart";
|
||||
reg = <0x10830000 0x100>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>,
|
||||
<&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_bus>;
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10980000 {
|
||||
compatible = "samsung,exynos8895-pinctrl";
|
||||
reg = <0x10980000 0x1000>;
|
||||
interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
hsi2c_1: i2c@10990000 {
|
||||
compatible = "samsung,exynos8895-hsi2c";
|
||||
reg = <0x10990000 0x1000>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK>;
|
||||
clock-names = "hsi2c";
|
||||
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&hsi2c1_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_2: i2c@109a0000 {
|
||||
compatible = "samsung,exynos8895-hsi2c";
|
||||
reg = <0x109a0000 0x1000>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK>;
|
||||
clock-names = "hsi2c";
|
||||
interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&hsi2c2_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_3: i2c@109b0000 {
|
||||
compatible = "samsung,exynos8895-hsi2c";
|
||||
reg = <0x109b0000 0x1000>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK>;
|
||||
clock-names = "hsi2c";
|
||||
interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&hsi2c3_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_4: i2c@109c0000 {
|
||||
compatible = "samsung,exynos8895-hsi2c";
|
||||
reg = <0x109c0000 0x1000>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK>;
|
||||
clock-names = "hsi2c";
|
||||
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&hsi2c4_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_0: spi@109d0000 {
|
||||
compatible = "samsung,exynos8895-spi",
|
||||
"samsung,exynos850-spi";
|
||||
|
|
|
|||
503
arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi
Normal file
503
arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,503 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source
|
||||
*
|
||||
* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
|
||||
* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
|
||||
*/
|
||||
|
||||
#include "exynos-pinctrl.h"
|
||||
|
||||
&pinctrl_alive {
|
||||
etc1: etc1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa0: gpa0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa1: gpa1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa2: gpa2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa3: gpa3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa4: gpa4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpq0: gpq0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_aud {
|
||||
gpb0: gpb0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb2: gpb2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_chub {
|
||||
gph0: gph0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph1: gph1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_cmgp {
|
||||
gpm0: gpm0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm1: gpm1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm2: gpm2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm3: gpm3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm4: gpm4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm5: gpm5-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm6: gpm6-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm7: gpm7-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm10: gpm10-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm11: gpm11-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm12: gpm12-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm13: gpm13-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm14: gpm14-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm15: gpm15-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm16: gpm16-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm17: gpm17-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm40: gpm40-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm41: gpm41-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm42: gpm42-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpm43: gpm43-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_fsys0 {
|
||||
gpf0: gpf0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_fsys1 {
|
||||
gpf1: gpf1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf2: gpf2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_peric0 {
|
||||
gpg0: gpg0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp0: gpp0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp1: gpp1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp2: gpp2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp3: gpp3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_peric1 {
|
||||
gpc0: gpc0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc1: gpc1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd0: gpd0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg3: gpg3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp4: gpp4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp5: gpp5-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpp6: gpp6-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_vts {
|
||||
gpt0: gpt0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
119
arch/arm64/boot/dts/exynos/exynos9810-starlte.dts
Normal file
119
arch/arm64/boot/dts/exynos/exynos9810-starlte.dts
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S9 (starlte/SM-G960F) device tree source
|
||||
*
|
||||
* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
|
||||
* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos9810.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Samsung Galaxy S9 (SM-G960F)";
|
||||
compatible = "samsung,starlte", "samsung,exynos9810";
|
||||
chassis-type = "handset";
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
framebuffer@cc000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
|
||||
width = <1440>;
|
||||
height = <2960>;
|
||||
stride = <(1440 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&key_power &key_voldown &key_volup &key_wink>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-key {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
voldown-key {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
volup-key {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* In stock firmware used for assistant. Map it as a camera button for now */
|
||||
wink-key {
|
||||
label = "Camera";
|
||||
linux,code = <KEY_CAMERA>;
|
||||
gpios = <&gpa0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x3c800000>,
|
||||
<0x0 0xc0000000 0x20000000>,
|
||||
<0x0 0xe1900000 0x1e700000>,
|
||||
<0x8 0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
framebuffer@cc000000 {
|
||||
reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
key_power: key-power-pins {
|
||||
samsung,pins = "gpa2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa0-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_volup: key-volup-pins {
|
||||
samsung,pins = "gpa0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_wink: key-wink-pins {
|
||||
samsung,pins = "gpa0-6";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
273
arch/arm64/boot/dts/exynos/exynos9810.dtsi
Normal file
273
arch/arm64/boot/dts/exynos/exynos9810.dtsi
Normal file
|
|
@ -0,0 +1,273 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Exynos 9810 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
|
||||
* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos9810";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
pinctrl0 = &pinctrl_alive;
|
||||
pinctrl1 = &pinctrl_aud;
|
||||
pinctrl2 = &pinctrl_chub;
|
||||
pinctrl3 = &pinctrl_cmgp;
|
||||
pinctrl4 = &pinctrl_fsys0;
|
||||
pinctrl5 = &pinctrl_fsys1;
|
||||
pinctrl6 = &pinctrl_peric0;
|
||||
pinctrl7 = &pinctrl_peric1;
|
||||
pinctrl8 = &pinctrl_vts;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
oscclk: osc-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk";
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
pmu-mongoose-m3 {
|
||||
compatible = "samsung,mongoose-pmu";
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu4>,
|
||||
<&cpu5>,
|
||||
<&cpu6>,
|
||||
<&cpu7>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x0 0x0 0x20000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chipid@10000000 {
|
||||
compatible = "samsung,exynos9810-chipid",
|
||||
"samsung,exynos850-chipid";
|
||||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10101000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x10101000 0x1000>,
|
||||
<0x10102000 0x1000>,
|
||||
<0x10104000 0x2000>,
|
||||
<0x10106000 0x2000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@10430000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x10430000 0x1000>;
|
||||
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10830000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x10830000 0x1000>;
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys0: pinctrl@11050000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x11050000 0x1000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys1: pinctrl@11430000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x11430000 0x1000>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_vts: pinctrl@13880000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x13880000 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_chub: pinctrl@13a80000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x13a80000 0x1000>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@14050000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x14050000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos9810-wakeup-eint",
|
||||
"samsung,exynos850-wakeup-eint",
|
||||
"samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@14060000 {
|
||||
compatible = "samsung,exynos9810-pmu",
|
||||
"samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x14060000 0x10000>;
|
||||
};
|
||||
|
||||
pinctrl_cmgp: pinctrl@14220000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x14220000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos9810-wakeup-eint",
|
||||
"samsung,exynos850-wakeup-eint",
|
||||
"samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_aud: pinctrl@17c60000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x17c60000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
/*
|
||||
* Non-updatable, broken stock Samsung bootloader does not
|
||||
* configure CNTFRQ_EL0
|
||||
*/
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "exynos9810-pinctrl.dtsi"
|
||||
#include "arm/samsung/exynos-syscon-restart.dtsi"
|
||||
115
arch/arm64/boot/dts/exynos/exynos990-r8s.dts
Normal file
115
arch/arm64/boot/dts/exynos/exynos990-r8s.dts
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 FE (r8s/SM-G780F) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Denzeel Oliva <wachiturroxd150@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Samsung Galaxy S20 FE";
|
||||
compatible = "samsung,r8s", "samsung,exynos990";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer0: framebuffer@f1000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0xf1000000 0 (1080 * 2400 * 4)>;
|
||||
width = <1080>;
|
||||
height = <2400>;
|
||||
stride = <(1080 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole - last block */
|
||||
<0x8 0x80000000 0x0 0xc0000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cont_splash_mem: framebuffer@f1000000 {
|
||||
reg = <0 0xf1000000 0 0x13c6800>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
abox_reserved: audio@f7fb0000 {
|
||||
reg = <0 0xf7fb0000 0 0x2a50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&key_power &key_voldown &key_volup>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-key {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
voldown-key {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
volup-key {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
key_power: key-power-pins {
|
||||
samsung,pins = "gpa2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa0-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_volup: key-volup-pins {
|
||||
samsung,pins = "gpa0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
98
arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi
Normal file
98
arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 Series device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer0: framebuffer@f1000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0xf1000000 0 (1440 * 3200 * 4)>;
|
||||
width = <1440>;
|
||||
height = <3200>;
|
||||
stride = <(1440 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cont_splash_mem: framebuffer@f1000000 {
|
||||
reg = <0 0xf1000000 0 0x1194000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
abox_reserved: audio@f7fb0000 {
|
||||
reg = <0 0xf7fb0000 0 0x2a50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&key_power &key_voldown &key_volup>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-key {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
voldown-key {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
volup-key {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
key_power: key-power-pins {
|
||||
samsung,pins = "gpa2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa0-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_volup: key-volup-pins {
|
||||
samsung,pins = "gpa0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
28
arch/arm64/boot/dts/exynos/exynos990-x1s.dts
Normal file
28
arch/arm64/boot/dts/exynos/exynos990-x1s.dts
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990-x1s-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
model = "Samsung Galaxy S20 5G";
|
||||
compatible = "samsung,x1s", "samsung,exynos990";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole */
|
||||
<0x8 0x80000000 0x2 0x7e800000>;
|
||||
};
|
||||
};
|
||||
28
arch/arm64/boot/dts/exynos/exynos990-x1slte.dts
Normal file
28
arch/arm64/boot/dts/exynos/exynos990-x1slte.dts
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 (x1slte/SM-G980F) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990-x1s-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
model = "Samsung Galaxy S20";
|
||||
compatible = "samsung,x1slte", "samsung,exynos990";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole */
|
||||
<0x8 0x80000000 0x1 0x7ec00000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -5,6 +5,7 @@
|
|||
* Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/samsung,exynos990.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -46,7 +47,14 @@ arm-a76-pmu {
|
|||
<&cpu5>;
|
||||
};
|
||||
|
||||
/* There's no PMU model for cluster2, which are the Mongoose cores. */
|
||||
mongoose-m5-pmu {
|
||||
compatible = "samsung,mongoose-pmu";
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-affinity = <&cpu6>,
|
||||
<&cpu7>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -199,6 +207,23 @@ pinctrl_peric1: pinctrl@10730000 {
|
|||
interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cmu_hsi0: clock-controller@10a00000 {
|
||||
compatible = "samsung,exynos990-cmu-hsi0";
|
||||
reg = <0x10a00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
|
||||
clock-names = "oscclk",
|
||||
"bus",
|
||||
"usb31drd",
|
||||
"usbdp_debug",
|
||||
"dpgtc";
|
||||
};
|
||||
|
||||
pinctrl_hsi1: pinctrl@13040000 {
|
||||
compatible = "samsung,exynos990-pinctrl";
|
||||
reg = <0x13040000 0x1000>;
|
||||
|
|
@ -227,10 +252,33 @@ wakeup-interrupt-controller {
|
|||
};
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@15860000 {
|
||||
compatible = "samsung,exynos990-pmu",
|
||||
"samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x15860000 0x10000>;
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x3a00>; /* SWRESET */
|
||||
mask = <0x2>; /* SWRESET_TRIGGER */
|
||||
value = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_cmgp: pinctrl@15c30000 {
|
||||
compatible = "samsung,exynos990-pinctrl";
|
||||
reg = <0x15c30000 0x1000>;
|
||||
};
|
||||
|
||||
cmu_top: clock-controller@1a330000 {
|
||||
compatible = "samsung,exynos990-cmu-top";
|
||||
reg = <0x1a330000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>;
|
||||
clock-names = "oscclk";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -183,6 +183,26 @@ cmu_misc: clock-controller@10020000 {
|
|||
"noc";
|
||||
};
|
||||
|
||||
watchdog_cl0: watchdog@10060000 {
|
||||
compatible = "samsung,exynosautov920-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xtcxo>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <0>;
|
||||
};
|
||||
|
||||
watchdog_cl1: watchdog@10070000 {
|
||||
compatible = "samsung,exynosautov920-wdt";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xtcxo>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -193,6 +213,69 @@ gic: interrupt-controller@10400000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spdma0: dma-controller@10180000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10180000 0x1000>;
|
||||
interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
spdma1: dma-controller@10190000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10190000 0x1000>;
|
||||
interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma0: dma-controller@101a0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101a0000 0x1000>;
|
||||
interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma1: dma-controller@101b0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101b0000 0x1000>;
|
||||
interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma2: dma-controller@101c0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101c0000 0x1000>;
|
||||
interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma3: dma-controller@101d0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101d0000 0x1000>;
|
||||
interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma4: dma-controller@101e0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101e0000 0x1000>;
|
||||
interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
||||
reg = <0x10800000 0x8000>;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "gs101-pinctrl.h"
|
||||
#include "gs101.dtsi"
|
||||
|
||||
|
|
@ -90,6 +91,89 @@ eeprom: eeprom@50 {
|
|||
&hsi2c_12 {
|
||||
status = "okay";
|
||||
/* TODO: add the devices once drivers exist */
|
||||
|
||||
usb-typec@25 {
|
||||
compatible = "maxim,max77759-tcpci", "maxim,max33359";
|
||||
reg = <0x25>;
|
||||
interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&typec_int>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
data-role = "dual";
|
||||
power-role = "dual";
|
||||
self-powered;
|
||||
try-power-role = "sink";
|
||||
op-sink-microwatt = <2600000>;
|
||||
slow-charger-loop;
|
||||
/*
|
||||
* max77759 operating in reverse boost mode (0xA) can
|
||||
* source up to 1.5A while extboost can only do ~1A.
|
||||
* Since extboost is the primary path, advertise 900mA.
|
||||
*/
|
||||
source-pdos = <PDO_FIXED(5000, 900,
|
||||
(PDO_FIXED_SUSPEND
|
||||
| PDO_FIXED_USB_COMM
|
||||
| PDO_FIXED_DATA_SWAP
|
||||
| PDO_FIXED_DUAL_ROLE))>;
|
||||
sink-pdos = <PDO_FIXED(5000, 3000,
|
||||
(PDO_FIXED_DATA_SWAP
|
||||
| PDO_FIXED_USB_COMM
|
||||
| PDO_FIXED_HIGHER_CAP
|
||||
| PDO_FIXED_DUAL_ROLE))
|
||||
PDO_FIXED(9000, 2200, 0)
|
||||
PDO_PPS_APDO(5000, 11000, 3000)>;
|
||||
sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
|
||||
IDH_PTYPE_DFP_HOST, 2, 0x18d1)
|
||||
VDO_CERT(0x0)
|
||||
VDO_PRODUCT(0x4ee1, 0x0)
|
||||
VDO_UFP(UFP_VDO_VER1_2,
|
||||
(DEV_USB2_CAPABLE
|
||||
| DEV_USB3_CAPABLE),
|
||||
UFP_RECEPTACLE, 0,
|
||||
AMA_VCONN_NOT_REQ, 0,
|
||||
UFP_ALTMODE_NOT_SUPP,
|
||||
UFP_USB32_GEN1)
|
||||
/* padding */ 0
|
||||
VDO_DFP(DFP_VDO_VER1_1,
|
||||
(HOST_USB2_CAPABLE
|
||||
| HOST_USB3_CAPABLE),
|
||||
DFP_RECEPTACLE, 0)>;
|
||||
sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
|
||||
0, 0, 0x18d1)
|
||||
VDO_CERT(0x0)
|
||||
VDO_PRODUCT(0x4ee1, 0x0)>;
|
||||
/*
|
||||
* Until bootloader is updated to set those two when
|
||||
* console is enabled, we disable PD here.
|
||||
*/
|
||||
pd-disable;
|
||||
typec-power-opmode = "default";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
usbc0_orien_sw: endpoint {
|
||||
remote-endpoint = <&usbdrd31_phy_orien_switch>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
usbc0_role_sw: endpoint {
|
||||
remote-endpoint = <&usbdrd31_dwc3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_far_alive {
|
||||
|
|
@ -106,6 +190,13 @@ key_volup: key-volup-pins {
|
|||
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
|
||||
};
|
||||
|
||||
typec_int: typec-int-pins {
|
||||
samsung,pins = "gpa8-2";
|
||||
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <GS101_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_gpio_alive {
|
||||
|
|
@ -142,9 +233,16 @@ &usbdrd31_dwc3 {
|
|||
role-switch-default-mode = "peripheral";
|
||||
maximum-speed = "super-speed-plus";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usbdrd31_dwc3_role_switch: endpoint {
|
||||
remote-endpoint = <&usbc0_role_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbdrd31_phy {
|
||||
orientation-switch;
|
||||
/* TODO: Update these once PMIC is implemented */
|
||||
pll-supply = <®_placeholder>;
|
||||
dvdd-usb20-supply = <®_placeholder>;
|
||||
|
|
@ -153,6 +251,12 @@ &usbdrd31_phy {
|
|||
vdda-usbdp-supply = <®_placeholder>;
|
||||
vddh-usbdp-supply = <®_placeholder>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usbdrd31_phy_orien_switch: endpoint {
|
||||
remote-endpoint = <&usbc0_orien_sw>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usi_uart {
|
||||
|
|
|
|||
|
|
@ -1267,7 +1267,7 @@ cmu_hsi0: clock-controller@11000000 {
|
|||
|
||||
usbdrd31_phy: phy@11100000 {
|
||||
compatible = "google,gs101-usb31drd-phy";
|
||||
reg = <0x11100000 0x0100>,
|
||||
reg = <0x11100000 0x0200>,
|
||||
<0x110f0000 0x0800>,
|
||||
<0x110e0000 0x2800>;
|
||||
reg-names = "phy", "pcs", "pma";
|
||||
|
|
@ -1302,6 +1302,9 @@ usbdrd31_dwc3: usb@0 {
|
|||
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,has-lpm-erratum;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
236
include/dt-bindings/clock/samsung,exynos990.h
Normal file
236
include/dt-bindings/clock/samsung,exynos990.h
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
*
|
||||
* Device Tree binding constants for Exynos990 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_FOUT_G3D_PLL 6
|
||||
#define CLK_FOUT_MMC_PLL 7
|
||||
#define CLK_MOUT_PLL_SHARED0 8
|
||||
#define CLK_MOUT_PLL_SHARED1 9
|
||||
#define CLK_MOUT_PLL_SHARED2 10
|
||||
#define CLK_MOUT_PLL_SHARED3 11
|
||||
#define CLK_MOUT_PLL_SHARED4 12
|
||||
#define CLK_MOUT_PLL_MMC 13
|
||||
#define CLK_MOUT_PLL_G3D 14
|
||||
#define CLK_MOUT_CMU_APM_BUS 15
|
||||
#define CLK_MOUT_CMU_AUD_CPU 16
|
||||
#define CLK_MOUT_CMU_BUS0_BUS 17
|
||||
#define CLK_MOUT_CMU_BUS1_BUS 18
|
||||
#define CLK_MOUT_CMU_BUS1_SSS 19
|
||||
#define CLK_MOUT_CMU_CIS_CLK0 20
|
||||
#define CLK_MOUT_CMU_CIS_CLK1 21
|
||||
#define CLK_MOUT_CMU_CIS_CLK2 22
|
||||
#define CLK_MOUT_CMU_CIS_CLK3 23
|
||||
#define CLK_MOUT_CMU_CIS_CLK4 24
|
||||
#define CLK_MOUT_CMU_CIS_CLK5 25
|
||||
#define CLK_MOUT_CMU_CMU_BOOST 26
|
||||
#define CLK_MOUT_CMU_CORE_BUS 27
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
|
||||
#define CLK_MOUT_CMU_CPUCL2_BUSP 31
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
|
||||
#define CLK_MOUT_CMU_CSIS_BUS 33
|
||||
#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
|
||||
#define CLK_MOUT_CMU_DNC_BUS 35
|
||||
#define CLK_MOUT_CMU_DNC_BUSM 36
|
||||
#define CLK_MOUT_CMU_DNS_BUS 37
|
||||
#define CLK_MOUT_CMU_DPU 38
|
||||
#define CLK_MOUT_CMU_DPU_ALT 39
|
||||
#define CLK_MOUT_CMU_DSP_BUS 40
|
||||
#define CLK_MOUT_CMU_G2D_G2D 41
|
||||
#define CLK_MOUT_CMU_G2D_MSCL 42
|
||||
#define CLK_MOUT_CMU_HPM 43
|
||||
#define CLK_MOUT_CMU_HSI0_BUS 44
|
||||
#define CLK_MOUT_CMU_HSI0_DPGTC 45
|
||||
#define CLK_MOUT_CMU_HSI0_USB31DRD 46
|
||||
#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
|
||||
#define CLK_MOUT_CMU_HSI1_BUS 48
|
||||
#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
|
||||
#define CLK_MOUT_CMU_HSI1_PCIE 50
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
|
||||
#define CLK_MOUT_CMU_HSI2_BUS 53
|
||||
#define CLK_MOUT_CMU_HSI2_PCIE 54
|
||||
#define CLK_MOUT_CMU_IPP_BUS 55
|
||||
#define CLK_MOUT_CMU_ITP_BUS 56
|
||||
#define CLK_MOUT_CMU_MCSC_BUS 57
|
||||
#define CLK_MOUT_CMU_MCSC_GDC 58
|
||||
#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
|
||||
#define CLK_MOUT_CMU_MFC0_MFC0 60
|
||||
#define CLK_MOUT_CMU_MFC0_WFD 61
|
||||
#define CLK_MOUT_CMU_MIF_BUSP 62
|
||||
#define CLK_MOUT_CMU_MIF_SWITCH 63
|
||||
#define CLK_MOUT_CMU_NPU_BUS 64
|
||||
#define CLK_MOUT_CMU_PERIC0_BUS 65
|
||||
#define CLK_MOUT_CMU_PERIC0_IP 66
|
||||
#define CLK_MOUT_CMU_PERIC1_BUS 67
|
||||
#define CLK_MOUT_CMU_PERIC1_IP 68
|
||||
#define CLK_MOUT_CMU_PERIS_BUS 69
|
||||
#define CLK_MOUT_CMU_SSP_BUS 70
|
||||
#define CLK_MOUT_CMU_TNR_BUS 71
|
||||
#define CLK_MOUT_CMU_VRA_BUS 72
|
||||
#define CLK_DOUT_CMU_APM_BUS 73
|
||||
#define CLK_DOUT_CMU_AUD_CPU 74
|
||||
#define CLK_DOUT_CMU_BUS0_BUS 75
|
||||
#define CLK_DOUT_CMU_BUS1_BUS 76
|
||||
#define CLK_DOUT_CMU_BUS1_SSS 77
|
||||
#define CLK_DOUT_CMU_CIS_CLK0 78
|
||||
#define CLK_DOUT_CMU_CIS_CLK1 79
|
||||
#define CLK_DOUT_CMU_CIS_CLK2 80
|
||||
#define CLK_DOUT_CMU_CIS_CLK3 81
|
||||
#define CLK_DOUT_CMU_CIS_CLK4 82
|
||||
#define CLK_DOUT_CMU_CIS_CLK5 83
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 84
|
||||
#define CLK_DOUT_CMU_CORE_BUS 85
|
||||
#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
|
||||
#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
|
||||
#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
|
||||
#define CLK_DOUT_CMU_CPUCL2_BUSP 89
|
||||
#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
|
||||
#define CLK_DOUT_CMU_CSIS_BUS 91
|
||||
#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
|
||||
#define CLK_DOUT_CMU_DNC_BUS 93
|
||||
#define CLK_DOUT_CMU_DNC_BUSM 94
|
||||
#define CLK_DOUT_CMU_DNS_BUS 95
|
||||
#define CLK_DOUT_CMU_DSP_BUS 96
|
||||
#define CLK_DOUT_CMU_G2D_G2D 97
|
||||
#define CLK_DOUT_CMU_G2D_MSCL 98
|
||||
#define CLK_DOUT_CMU_G3D_SWITCH 99
|
||||
#define CLK_DOUT_CMU_HPM 100
|
||||
#define CLK_DOUT_CMU_HSI0_BUS 101
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 102
|
||||
#define CLK_DOUT_CMU_HSI0_USB31DRD 103
|
||||
#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
|
||||
#define CLK_DOUT_CMU_HSI1_BUS 105
|
||||
#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
|
||||
#define CLK_DOUT_CMU_HSI1_PCIE 107
|
||||
#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
|
||||
#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
|
||||
#define CLK_DOUT_CMU_HSI2_BUS 110
|
||||
#define CLK_DOUT_CMU_HSI2_PCIE 111
|
||||
#define CLK_DOUT_CMU_IPP_BUS 112
|
||||
#define CLK_DOUT_CMU_ITP_BUS 113
|
||||
#define CLK_DOUT_CMU_MCSC_BUS 114
|
||||
#define CLK_DOUT_CMU_MCSC_GDC 115
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
|
||||
#define CLK_DOUT_CMU_MFC0_MFC0 117
|
||||
#define CLK_DOUT_CMU_MFC0_WFD 118
|
||||
#define CLK_DOUT_CMU_MIF_BUSP 119
|
||||
#define CLK_DOUT_CMU_NPU_BUS 120
|
||||
#define CLK_DOUT_CMU_OTP 121
|
||||
#define CLK_DOUT_CMU_PERIC0_BUS 122
|
||||
#define CLK_DOUT_CMU_PERIC0_IP 123
|
||||
#define CLK_DOUT_CMU_PERIC1_BUS 124
|
||||
#define CLK_DOUT_CMU_PERIC1_IP 125
|
||||
#define CLK_DOUT_CMU_PERIS_BUS 126
|
||||
#define CLK_DOUT_CMU_SSP_BUS 127
|
||||
#define CLK_DOUT_CMU_TNR_BUS 128
|
||||
#define CLK_DOUT_CMU_VRA_BUS 129
|
||||
#define CLK_DOUT_CMU_DPU 130
|
||||
#define CLK_DOUT_CMU_DPU_ALT 131
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV2 132
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV3 133
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV4 134
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV2 135
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV3 136
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV4 137
|
||||
#define CLK_DOUT_CMU_SHARED2_DIV2 138
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV2 139
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV3 140
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV4 141
|
||||
#define CLK_GOUT_CMU_G3D_BUS 142
|
||||
#define CLK_GOUT_CMU_MIF_SWITCH 143
|
||||
#define CLK_GOUT_CMU_APM_BUS 144
|
||||
#define CLK_GOUT_CMU_AUD_CPU 145
|
||||
#define CLK_GOUT_CMU_BUS0_BUS 146
|
||||
#define CLK_GOUT_CMU_BUS1_BUS 147
|
||||
#define CLK_GOUT_CMU_BUS1_SSS 148
|
||||
#define CLK_GOUT_CMU_CIS_CLK0 149
|
||||
#define CLK_GOUT_CMU_CIS_CLK1 150
|
||||
#define CLK_GOUT_CMU_CIS_CLK2 151
|
||||
#define CLK_GOUT_CMU_CIS_CLK3 152
|
||||
#define CLK_GOUT_CMU_CIS_CLK4 153
|
||||
#define CLK_GOUT_CMU_CIS_CLK5 154
|
||||
#define CLK_GOUT_CMU_CORE_BUS 155
|
||||
#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
|
||||
#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
|
||||
#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
|
||||
#define CLK_GOUT_CMU_CPUCL2_BUSP 159
|
||||
#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
|
||||
#define CLK_GOUT_CMU_CSIS_BUS 161
|
||||
#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
|
||||
#define CLK_GOUT_CMU_DNC_BUS 163
|
||||
#define CLK_GOUT_CMU_DNC_BUSM 164
|
||||
#define CLK_GOUT_CMU_DNS_BUS 165
|
||||
#define CLK_GOUT_CMU_DPU 166
|
||||
#define CLK_GOUT_CMU_DPU_BUS 167
|
||||
#define CLK_GOUT_CMU_DSP_BUS 168
|
||||
#define CLK_GOUT_CMU_G2D_G2D 169
|
||||
#define CLK_GOUT_CMU_G2D_MSCL 170
|
||||
#define CLK_GOUT_CMU_G3D_SWITCH 171
|
||||
#define CLK_GOUT_CMU_HPM 172
|
||||
#define CLK_GOUT_CMU_HSI0_BUS 173
|
||||
#define CLK_GOUT_CMU_HSI0_DPGTC 174
|
||||
#define CLK_GOUT_CMU_HSI0_USB31DRD 175
|
||||
#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
|
||||
#define CLK_GOUT_CMU_HSI1_BUS 177
|
||||
#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
|
||||
#define CLK_GOUT_CMU_HSI1_PCIE 179
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
|
||||
#define CLK_GOUT_CMU_HSI2_BUS 182
|
||||
#define CLK_GOUT_CMU_HSI2_PCIE 183
|
||||
#define CLK_GOUT_CMU_IPP_BUS 184
|
||||
#define CLK_GOUT_CMU_ITP_BUS 185
|
||||
#define CLK_GOUT_CMU_MCSC_BUS 186
|
||||
#define CLK_GOUT_CMU_MCSC_GDC 187
|
||||
#define CLK_GOUT_CMU_MFC0_MFC0 188
|
||||
#define CLK_GOUT_CMU_MFC0_WFD 189
|
||||
#define CLK_GOUT_CMU_MIF_BUSP 190
|
||||
#define CLK_GOUT_CMU_NPU_BUS 191
|
||||
#define CLK_GOUT_CMU_PERIC0_BUS 192
|
||||
#define CLK_GOUT_CMU_PERIC0_IP 193
|
||||
#define CLK_GOUT_CMU_PERIC1_BUS 194
|
||||
#define CLK_GOUT_CMU_PERIC1_IP 195
|
||||
#define CLK_GOUT_CMU_PERIS_BUS 196
|
||||
#define CLK_GOUT_CMU_SSP_BUS 197
|
||||
#define CLK_GOUT_CMU_TNR_BUS 198
|
||||
#define CLK_GOUT_CMU_VRA_BUS 199
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_HSI0_BUS_USER 1
|
||||
#define CLK_MOUT_HSI0_USB31DRD_USER 2
|
||||
#define CLK_MOUT_HSI0_USBDP_DEBUG_USER 3
|
||||
#define CLK_MOUT_HSI0_DPGTC_USER 4
|
||||
#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK 5
|
||||
#define CLK_GOUT_HSI0_DP_LINK_PCLK 6
|
||||
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 7
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK 8
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK 9
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK 10
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 11
|
||||
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 12
|
||||
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 13
|
||||
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 14
|
||||
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 15
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40 16
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL 17
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB 18
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK 19
|
||||
#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
|
||||
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
|
||||
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user