drm/amdgpu/gmc11: don't touch gfxhub registers during S0ix

gfxhub registers are part of gfx IP and should not need to be
changed.  Doing so without disabling gfxoff can hang the gfx IP.

v2: add comments explaining why we can skip the interrupt
    control for S0i3

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2022-11-09 16:20:26 -05:00
parent d5d29009b8
commit 735c706468

View File

@ -64,13 +64,25 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
/* MM HUB */
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
/* GFX HUB */
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
/* This works because this interrupt is only
* enabled at init/resume and disabled in
* fini/suspend, so the overall state doesn't
* change over the course of suspend/resume.
*/
if (!adev->in_s0ix)
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
break;
case AMDGPU_IRQ_STATE_ENABLE:
/* MM HUB */
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
/* GFX HUB */
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
/* This works because this interrupt is only
* enabled at init/resume and disabled in
* fini/suspend, so the overall state doesn't
* change over the course of suspend/resume.
*/
if (!adev->in_s0ix)
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
break;
default:
break;