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drm/amdgpu/gmc11: don't touch gfxhub registers during S0ix
gfxhub registers are part of gfx IP and should not need to be
changed. Doing so without disabling gfxoff can hang the gfx IP.
v2: add comments explaining why we can skip the interrupt
control for S0i3
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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@ -64,13 +64,25 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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/* MM HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
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/* GFX HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
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/* This works because this interrupt is only
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* enabled at init/resume and disabled in
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* fini/suspend, so the overall state doesn't
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* change over the course of suspend/resume.
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*/
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if (!adev->in_s0ix)
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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/* MM HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
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/* GFX HUB */
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
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/* This works because this interrupt is only
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* enabled at init/resume and disabled in
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* fini/suspend, so the overall state doesn't
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* change over the course of suspend/resume.
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*/
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if (!adev->in_s0ix)
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amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
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break;
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default:
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break;
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