dt-bindings: watchdog: qcom-wdt: merge MSM timer

Merge Qualcomm MSM timer bindings into watchdog, because the timer
compatibles are already included here and the hardware is quite similar.

While converting the MSM timer bindings, adjust clock-frequency
property to take only one frequency, instead of two, because:
1. DT schema does not allow to frequencies,
2. The Linux timer driver reads only first frequency.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221212163532.142533-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Krzysztof Kozlowski 2023-01-13 11:33:45 +01:00 committed by Wim Van Sebroeck
parent 7c631cdff3
commit 7333185348
2 changed files with 49 additions and 47 deletions

View File

@ -1,47 +0,0 @@
* MSM Timer
Properties:
- compatible : Should at least contain "qcom,msm-timer". More specific
properties specify which subsystem the timers are paired with.
"qcom,kpss-timer" - krait subsystem
"qcom,scss-timer" - scorpion subsystem
- interrupts : Interrupts for the debug timer, the first general purpose
timer, and optionally a second general purpose timer, and
optionally as well, 2 watchdog interrupts, in that order.
- reg : Specifies the base address of the timer registers.
- clocks: Reference to the parent clocks, one per output clock. The parents
must appear in the same order as the clock names.
- clock-names: The name of the clocks as free-form strings. They should be in
the same order as the clocks.
- clock-frequency : The frequency of the debug timer and the general purpose
timer(s) in Hz in that order.
Optional:
- cpu-offset : per-cpu offset used when the timer is accessed without the
CPU remapping facilities. The offset is
cpu-offset + (0x10000 * cpu-nr).
Example:
timer@200a000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>,
<1 4 0x301>,
<1 5 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <19200000>,
<32768>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x40000>;
};

View File

@ -10,6 +10,9 @@ maintainers:
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
properties:
$nodename:
pattern: "^(watchdog|timer)@[0-9a-f]+$"
compatible:
oneOf:
- items:
@ -48,6 +51,20 @@ properties:
clocks:
maxItems: 1
clock-names:
items:
- const: sleep
clock-frequency:
description:
The frequency of the general purpose timer in Hz.
cpu-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Per-CPU offset used when the timer is accessed without the CPU remapping
facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
interrupts:
minItems: 1
maxItems: 5
@ -67,12 +84,27 @@ allOf:
const: qcom,kpss-wdt
then:
properties:
clock-frequency: false
cpu-offset: false
interrupts:
minItems: 1
items:
- description: Bark
- description: Bite
else:
properties:
interrupts:
minItems: 3
items:
- description: Debug
- description: First general purpose timer
- description: Second general purpose timer
- description: First watchdog
- description: Second watchdog
required:
- clock-frequency
unevaluatedProperties: false
examples:
@ -86,3 +118,20 @@ examples:
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <10>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@200a000 {
compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <25000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};