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ASoC: meson: aiu-formatter-i2s: remove pipeline reset from prepare
'aiu-fifo-i2s' (DAI FE) already resets the I2S pipeline in 'aiu_fifo_i2s_trigger' for all relevant trigger scenarios, right before starting the FIFO. Since the DAI triggering order is the default one (FE before BE), the reset performed in 'aiu_formatter_i2s_prepare' happens after the FIFO has already been reset and started, which corrupts playback in 24-bit mode. Remove the duplicated reset from the formatter. Signed-off-by: Valerio Setti <vsetti@baylibre.com> Link: https://patch.msgid.link/20260702-fix-24-bit-i2s-playback-v2-1-9c008ff0b211@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -13,7 +13,6 @@
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#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
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#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
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#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
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#define AIU_RST_SOFT_I2S_FAST BIT(0)
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#define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
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@ -55,11 +54,11 @@ static int aiu_formatter_i2s_prepare(struct regmap *map,
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{
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/* Always operate in split (classic interleaved) mode */
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unsigned int desc = 0;
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unsigned int tmp;
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/* Reset required to update the pipeline */
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regmap_write(map, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
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regmap_read(map, AIU_I2S_SYNC, &tmp);
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/*
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* Pipeline reset is already implemented in aiu_fifo_i2s_trigger() at
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* trigger time.
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*/
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switch (ts->physical_width) {
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case 16: /* Nothing to do */
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