ASoC: meson: aiu-formatter-i2s: remove pipeline reset from prepare

'aiu-fifo-i2s' (DAI FE) already resets the I2S pipeline in
'aiu_fifo_i2s_trigger' for all relevant trigger scenarios, right
before starting the FIFO. Since the DAI triggering order is the
default one (FE before BE), the reset performed in
'aiu_formatter_i2s_prepare' happens after the FIFO has already been
reset and started, which corrupts playback in 24-bit mode. Remove
the duplicated reset from the formatter.

Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Link: https://patch.msgid.link/20260702-fix-24-bit-i2s-playback-v2-1-9c008ff0b211@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Valerio Setti 2026-07-02 23:31:46 +02:00 committed by Mark Brown
parent 4a7c920458
commit 72fe2ef11d
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0

View File

@ -13,7 +13,6 @@
#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
#define AIU_RST_SOFT_I2S_FAST BIT(0)
#define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
@ -55,11 +54,11 @@ static int aiu_formatter_i2s_prepare(struct regmap *map,
{
/* Always operate in split (classic interleaved) mode */
unsigned int desc = 0;
unsigned int tmp;
/* Reset required to update the pipeline */
regmap_write(map, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
regmap_read(map, AIU_I2S_SYNC, &tmp);
/*
* Pipeline reset is already implemented in aiu_fifo_i2s_trigger() at
* trigger time.
*/
switch (ts->physical_width) {
case 16: /* Nothing to do */