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dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema
Move APQ8084 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. After moving the qcom,pcie.yaml becames empty thus can be entirely removed. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-12-873721599754@oss.qualcomm.com
This commit is contained in:
Krzysztof Kozlowski
Manivannan Sadhasivam
parent
0eaa8d1c36
commit
72b3943028
109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
Normal file
109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
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@ -0,0 +1,109 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm APQ8084 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,pcie-apq8084
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: config
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- const: mhi
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: iface # Configuration AHB clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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- const: aux
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: core
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vdda-supply:
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description: A phandle to the core analog power supply
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required:
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- power-domains
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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pcie@fc520000 {
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compatible = "qcom,pcie-apq8084";
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reg = <0xfc520000 0x2000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff002000 0x2000>;
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reg-names = "parf", "dbi", "elbi", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
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<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc 324>,
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<&gcc 325>,
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<&gcc 327>,
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<&gcc 323>;
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clock-names = "iface", "master_bus", "slave_bus", "aux";
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resets = <&gcc 81>;
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reset-names = "core";
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power-domains = <&gcc 1>;
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vdda-supply = <&pma8084_l3>;
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phys = <&pciephy0>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_pins_default>;
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pinctrl-names = "default";
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};
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@ -1,227 +0,0 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI express root complex
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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description: |
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Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
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PCIe IP.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,pcie-apq8084
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reg:
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minItems: 4
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 6
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interrupts:
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minItems: 1
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maxItems: 9
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interrupt-names:
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minItems: 1
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maxItems: 9
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iommu-map:
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minItems: 1
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maxItems: 16
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# Common definitions for clocks, clock-names and reset.
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# Platform constraints are described later.
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clocks:
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minItems: 3
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maxItems: 13
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clock-names:
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minItems: 3
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maxItems: 13
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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resets:
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minItems: 1
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maxItems: 12
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reset-names:
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minItems: 1
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maxItems: 12
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vdda-supply:
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description: A phandle to the core analog power supply
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pciephy
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power-domains:
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maxItems: 1
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perst-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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required-opps:
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maxItems: 1
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wake-gpios:
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description: GPIO controlled connection to WAKE# signal
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: iface # Configuration AHB clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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- const: aux # Auxiliary (AUX) clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: core # Core reset
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-msm8996
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then:
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required:
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- resets
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- reset-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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then:
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properties:
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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pcie@fc520000 {
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compatible = "qcom,pcie-apq8084";
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reg = <0xfc520000 0x2000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff002000 0x2000>;
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reg-names = "parf", "dbi", "elbi", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
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<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc 324>,
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<&gcc 325>,
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<&gcc 327>,
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<&gcc 323>;
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clock-names = "iface", "master_bus", "slave_bus", "aux";
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resets = <&gcc 81>;
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reset-names = "core";
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power-domains = <&gcc 1>;
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vdda-supply = <&pma8084_l3>;
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phys = <&pciephy0>;
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phy-names = "pciephy";
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perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_pins_default>;
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pinctrl-names = "default";
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};
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...
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