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x86/msr: Switch rdmsrl() users to rdmsrq()

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rdmsrl() is a deprecated synonym for rdmsrq(). Switch its users to
rdmsrq().

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: "K. Y. Srinivasan" <kys@microsoft.com>
Cc: Haiyang Zhang <haiyangz@microsoft.com>
Cc: Wei Liu <wei.liu@kernel.org>
Cc: Dexuan Cui <decui@microsoft.com>
Cc: Long Li <longli@microsoft.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Link: https://patch.msgid.link/20260608082809.3492719-2-jgross@suse.com
This commit is contained in:
Juergen Gross 2026-06-08 10:28:06 +02:00 committed by Ingo Molnar
parent cdd2c4133a
commit 72ac0e45c2
4 changed files with 5 additions and 5 deletions
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2
arch/x86/events/amd/uncore.c
View File

@ -966,7 +966,7 @@ static void amd_uncore_umc_read(struct perf_event *event)
* UMC counters do not have RDPMC assignments. Read counts directly
* from the corresponding PERF_CTR.
*/
rdmsrl(hwc->event_base, new);
rdmsrq(hwc->event_base, new);
/*
* Unlike the other uncore counters, UMC counters saturate and set the

2
arch/x86/kernel/cpu/resctrl/monitor.c
View File

@ -301,7 +301,7 @@ static int __cntr_id_read(u32 cntr_id, u64 *val)
* is set if the counter data is unavailable.
*/
wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id);
rdmsrl(MSR_IA32_QM_CTR, msr_val);
rdmsrq(MSR_IA32_QM_CTR, msr_val);
if (msr_val & RMID_VAL_ERROR)
return -EIO;

2
drivers/hv/mshv_vtl_main.c
View File

@ -598,7 +598,7 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set)
if (set)
wrmsrl(reg_table[i].msr_addr, *reg64);
else
rdmsrl(reg_table[i].msr_addr, *reg64);
rdmsrq(reg_table[i].msr_addr, *reg64);
}
return 0;
}

4
drivers/idle/intel_idle.c
View File

@ -2370,7 +2370,7 @@ static void intel_c1_demotion_toggle(void *enable)
{
unsigned long long msr_val;
rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
/*
* Enable/disable C1 undemotion along with C1 demotion, as this is the
* most sensible configuration in general.
@ -2410,7 +2410,7 @@ static ssize_t intel_c1_demotion_show(struct device *dev,
* Read the MSR value for a CPU and assume it is the same for all CPUs. Any other
* configuration would be a BIOS bug.
*/
rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val);
return sysfs_emit(buf, "%d\n", !!(msr_val & NHM_C1_AUTO_DEMOTE));
}
static DEVICE_ATTR_RW(intel_c1_demotion);