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drm/amd/display: [FW Promotion] Release 0.1.48.0

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[Why&How]
Introduce DMUB IHC command.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Taimur Hassan 2026-02-12 16:49:15 -05:00 committed by Alex Deucher
parent 29c9087b96
commit 72835a05db
1 changed files with 54 additions and 0 deletions
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54
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
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@ -1897,6 +1897,10 @@ enum dmub_cmd_type {
*/
DMUB_CMD__PR = 94,
/**
* Command type used for all IHC commands.
*/
DMUB_CMD__IHC = 95,
/**
* Command type use for VBIOS shared commands.
@ -4959,6 +4963,52 @@ union dmub_replay_cmd_set {
struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
};
/**
* IHC command sub-types.
*/
enum dmub_cmd_ihc_type {
/**
* Set DIG HDCP interrupt destination.
*/
DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0,
};
/**
* Data passed from driver to FW in a DMUB_CMD__IHC command.
*/
struct dmub_cmd_ihc_data {
/**
* DIG engine ID (0-3).
*/
uint8_t dig_id;
/**
* 1 = route to DMU, 0 = route to CPU.
*/
uint8_t to_dmu : 1;
/**
* Reserved bits.
*/
uint8_t reserved : 7;
/**
* Padding.
*/
uint8_t pad[2];
};
/**
* Definition of a DMUB_CMD__IHC command.
*/
struct dmub_rb_cmd_ihc {
/**
* Command header.
*/
struct dmub_cmd_header header;
/**
* IHC command data.
*/
struct dmub_cmd_ihc_data data;
};
/**
* SMART POWER OLED command sub-types.
*/
@ -7142,6 +7192,10 @@ union dmub_rb_cmd {
struct dmub_rb_cmd_pr_update_state pr_update_state;
struct dmub_rb_cmd_pr_general_cmd pr_general_cmd;
/**
* Definition of a DMUB_CMD__IHC command.
*/
struct dmub_rb_cmd_ihc ihc;
};
/**