diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c index ffa27f66bba7..f28c7ae0e8c2 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c @@ -381,7 +381,7 @@ static ssize_t sched_group_engines_read(struct file *file, char __user *buf, if (group < num_groups) { for_each_hw_engine(hwe, gt, id) { - u8 guc_class = xe_engine_class_to_guc_class(hwe->class); + u8 guc_class = xe_hwe_to_guc_class(hwe); u32 mask = groups[group].engines[guc_class]; if (mask & BIT(hwe->logical_instance)) { diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c index e8458d63742d..cf117bf52d41 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c @@ -471,7 +471,7 @@ static void pf_sched_group_media_slices(struct xe_gt *gt, struct guc_sched_group return; for_each_hw_engine(hwe, gt, id) { - u8 guc_class = xe_engine_class_to_guc_class(hwe->class); + u8 guc_class = xe_hwe_to_guc_class(hwe); switch (hwe->class) { case XE_ENGINE_CLASS_VIDEO_DECODE: diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h index 02514914f404..12faf0ba7229 100644 --- a/drivers/gpu/drm/xe/xe_guc.h +++ b/drivers/gpu/drm/xe/xe_guc.h @@ -67,26 +67,7 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc); int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len); #endif -static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class) -{ - switch (class) { - case XE_ENGINE_CLASS_RENDER: - return GUC_RENDER_CLASS; - case XE_ENGINE_CLASS_VIDEO_DECODE: - return GUC_VIDEO_CLASS; - case XE_ENGINE_CLASS_VIDEO_ENHANCE: - return GUC_VIDEOENHANCE_CLASS; - case XE_ENGINE_CLASS_COPY: - return GUC_BLITTER_CLASS; - case XE_ENGINE_CLASS_COMPUTE: - return GUC_COMPUTE_CLASS; - case XE_ENGINE_CLASS_OTHER: - return GUC_GSC_OTHER_CLASS; - default: - XE_WARN_ON(class); - return -1; - } -} +u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe); static inline struct xe_gt *guc_to_gt(struct xe_guc *guc) { diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 6910179aff48..86b3261704bd 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -279,7 +279,7 @@ static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class) u32 mask = 0; for_each_hw_engine(hwe, gt, id) - if (xe_engine_class_to_guc_class(hwe->class) == guc_class) + if (xe_hwe_to_guc_class(hwe) == guc_class) mask |= BIT(hwe->instance); return mask; @@ -503,6 +503,27 @@ static void fill_engine_enable_masks(struct xe_gt *gt, engine_enable_mask(gt, guc_class)); } +u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe) +{ + switch (hwe->class) { + case XE_ENGINE_CLASS_RENDER: + return GUC_RENDER_CLASS; + case XE_ENGINE_CLASS_VIDEO_DECODE: + return GUC_VIDEO_CLASS; + case XE_ENGINE_CLASS_VIDEO_ENHANCE: + return GUC_VIDEOENHANCE_CLASS; + case XE_ENGINE_CLASS_COPY: + return GUC_BLITTER_CLASS; + case XE_ENGINE_CLASS_COMPUTE: + return GUC_COMPUTE_CLASS; + case XE_ENGINE_CLASS_OTHER: + return GUC_GSC_OTHER_CLASS; + default: + XE_WARN_ON(hwe->class); + return -1; + } +} + /* * Write the offsets corresponding to the golden LRCs. The actual data is * populated later by guc_golden_lrc_populate() @@ -573,7 +594,7 @@ static void guc_mapping_table_init(struct xe_gt *gt, for_each_hw_engine(hwe, gt, id) { u8 guc_class; - guc_class = xe_engine_class_to_guc_class(hwe->class); + guc_class = xe_hwe_to_guc_class(hwe); info_map_write(xe, info_map, mapping_table[guc_class][hwe->logical_instance], hwe->instance); @@ -828,7 +849,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) * 2. Record in the header (ads.reg_state_list) the address * location and number of entries */ - gc = xe_engine_class_to_guc_class(hwe->class); + gc = xe_hwe_to_guc_class(hwe); ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr); ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count); diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 1a019137ddf4..3f287dd5e34e 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -440,7 +440,7 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc) * to be extended */ for_each_hw_engine(hwe, gt, id) { - if (xe_engine_class_to_guc_capture_class(hwe->class) == + if (xe_hwe_to_guc_capture_class(hwe) == GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE) { has_rcs_ccs = true; break; @@ -818,7 +818,7 @@ static int guc_capture_output_size_est(struct xe_guc *guc) for_each_hw_engine(hwe, gt, id) { enum guc_capture_list_class_type capture_class; - capture_class = xe_engine_class_to_guc_capture_class(hwe->class); + capture_class = xe_hwe_to_guc_capture_class(hwe); capture_size += sizeof(struct guc_state_capture_group_header_t) + (3 * sizeof(struct guc_state_capture_header_t)); @@ -1626,7 +1626,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot if (!new) return; - capture_class = xe_engine_class_to_guc_capture_class(hwe->class); + capture_class = xe_hwe_to_guc_capture_class(hwe); for (type = GUC_STATE_CAPTURE_TYPE_GLOBAL; type < GUC_STATE_CAPTURE_TYPE_MAX; type++) { struct gcap_reg_list_info *reginfo = &new->reginfo[type]; /* @@ -1668,7 +1668,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot } } - new->eng_class = xe_engine_class_to_guc_class(hwe->class); + new->eng_class = xe_hwe_to_guc_class(hwe); new->eng_inst = hwe->instance; new->guc_id = guc_id; new->lrca = lrca; @@ -1832,7 +1832,7 @@ void xe_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, struct drm xe_gt_assert(gt, snapshot->hwe); - capture_class = xe_engine_class_to_guc_capture_class(snapshot->hwe->class); + capture_class = xe_hwe_to_guc_capture_class(snapshot->hwe); drm_printf(p, "%s (physical), logical instance=%d\n", snapshot->name ? snapshot->name : "", @@ -1904,7 +1904,7 @@ xe_guc_capture_get_matching_and_lock(struct xe_exec_queue *q) for_each_hw_engine(hwe, q->gt, id) { if (hwe != q->hwe) continue; - guc_class = xe_engine_class_to_guc_class(hwe->class); + guc_class = xe_hwe_to_guc_class(hwe); break; } diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h index dca97d52b192..eb954f4d1ffd 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.h +++ b/drivers/gpu/drm/xe/xe_guc_capture.h @@ -35,9 +35,9 @@ static inline enum guc_capture_list_class_type xe_guc_class_to_capture_class(u16 } static inline enum guc_capture_list_class_type -xe_engine_class_to_guc_capture_class(enum xe_engine_class class) +xe_hwe_to_guc_capture_class(struct xe_hw_engine *hwe) { - return xe_guc_class_to_capture_class(xe_engine_class_to_guc_class(class)); + return xe_guc_class_to_capture_class(xe_hwe_to_guc_class(hwe)); } void xe_guc_capture_process(struct xe_guc *guc); diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c index f43ca1c76f75..c3a5fa80388b 100644 --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c @@ -27,7 +27,7 @@ static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_eng { struct xe_guc_engine_activity *engine_activity = &guc->engine_activity; struct engine_activity_buffer *buffer; - u16 guc_class = xe_engine_class_to_guc_class(hwe->class); + u16 guc_class = xe_hwe_to_guc_class(hwe); size_t offset; if (engine_activity->num_functions) { @@ -150,7 +150,7 @@ static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine { struct xe_guc *guc = &hwe->gt->uc.guc; struct engine_activity_group *eag = &guc->engine_activity.eag[index]; - u16 guc_class = xe_engine_class_to_guc_class(hwe->class); + u16 guc_class = xe_hwe_to_guc_class(hwe); return &eag->engine[guc_class][hwe->logical_instance]; } diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index e5fcb1f21115..68e484b16383 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -984,7 +984,7 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type) memset(&info, 0, sizeof(info)); info.context_idx = q->guc->id; - info.engine_class = xe_engine_class_to_guc_class(q->class); + info.engine_class = xe_hwe_to_guc_class(q->hwe); info.engine_submit_mask = q->logical_mask; info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));