mirror of
https://github.com/torvalds/linux.git
synced 2026-05-27 16:44:58 +02:00
Merge branch 'master' into mm-stable
This commit is contained in:
Andrew Morton
commit
71f6861cbf
|
|
@ -22,6 +22,7 @@ Date: Oct 25, 2019
|
|||
KernelVersion: 5.6.0
|
||||
Contact: dmaengine@vger.kernel.org
|
||||
Description: The largest number of work descriptors in a batch.
|
||||
It's not visible when the device does not support batch.
|
||||
|
||||
What: /sys/bus/dsa/devices/dsa<m>/max_work_queues_size
|
||||
Date: Oct 25, 2019
|
||||
|
|
@ -49,6 +50,8 @@ Description: The total number of read buffers supported by this device.
|
|||
The read buffers represent resources within the DSA
|
||||
implementation, and these resources are allocated by engines to
|
||||
support operations. See DSA spec v1.2 9.2.4 Total Read Buffers.
|
||||
It's not visible when the device does not support Read Buffer
|
||||
allocation control.
|
||||
|
||||
What: /sys/bus/dsa/devices/dsa<m>/max_transfer_size
|
||||
Date: Oct 25, 2019
|
||||
|
|
@ -122,6 +125,8 @@ Contact: dmaengine@vger.kernel.org
|
|||
Description: The maximum number of read buffers that may be in use at
|
||||
one time by operations that access low bandwidth memory in the
|
||||
device. See DSA spec v1.2 9.2.8 GENCFG on Global Read Buffer Limit.
|
||||
It's not visible when the device does not support Read Buffer
|
||||
allocation control.
|
||||
|
||||
What: /sys/bus/dsa/devices/dsa<m>/cmd_status
|
||||
Date: Aug 28, 2020
|
||||
|
|
@ -205,6 +210,7 @@ KernelVersion: 5.10.0
|
|||
Contact: dmaengine@vger.kernel.org
|
||||
Description: The max batch size for this workqueue. Cannot exceed device
|
||||
max batch size. Configurable parameter.
|
||||
It's not visible when the device does not support batch.
|
||||
|
||||
What: /sys/bus/dsa/devices/wq<m>.<n>/ats_disable
|
||||
Date: Nov 13, 2020
|
||||
|
|
@ -250,6 +256,8 @@ KernelVersion: 5.17.0
|
|||
Contact: dmaengine@vger.kernel.org
|
||||
Description: Enable the use of global read buffer limit for the group. See DSA
|
||||
spec v1.2 9.2.18 GRPCFG Use Global Read Buffer Limit.
|
||||
It's not visible when the device does not support Read Buffer
|
||||
allocation control.
|
||||
|
||||
What: /sys/bus/dsa/devices/group<m>.<n>/read_buffers_allowed
|
||||
Date: Dec 10, 2021
|
||||
|
|
@ -258,6 +266,8 @@ Contact: dmaengine@vger.kernel.org
|
|||
Description: Indicates max number of read buffers that may be in use at one time
|
||||
by all engines in the group. See DSA spec v1.2 9.2.18 GRPCFG Read
|
||||
Buffers Allowed.
|
||||
It's not visible when the device does not support Read Buffer
|
||||
allocation control.
|
||||
|
||||
What: /sys/bus/dsa/devices/group<m>.<n>/read_buffers_reserved
|
||||
Date: Dec 10, 2021
|
||||
|
|
@ -266,6 +276,8 @@ Contact: dmaengine@vger.kernel.org
|
|||
Description: Indicates the number of Read Buffers reserved for the use of
|
||||
engines in the group. See DSA spec v1.2 9.2.18 GRPCFG Read Buffers
|
||||
Reserved.
|
||||
It's not visible when the device does not support Read Buffer
|
||||
allocation control.
|
||||
|
||||
What: /sys/bus/dsa/devices/group<m>.<n>/desc_progress_limit
|
||||
Date: Sept 14, 2022
|
||||
|
|
|
|||
|
|
@ -1050,6 +1050,11 @@
|
|||
them frequently to increase the rate of SLB faults
|
||||
on kernel addresses.
|
||||
|
||||
stress_hpt [PPC]
|
||||
Limits the number of kernel HPT entries in the hash
|
||||
page table to increase the rate of hash page table
|
||||
faults on kernel addresses.
|
||||
|
||||
disable= [IPV6]
|
||||
See Documentation/networking/ipv6.rst.
|
||||
|
||||
|
|
@ -2308,7 +2313,13 @@
|
|||
Provide an override to the IOAPIC-ID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table.
|
||||
By default, PCI segment is 0, and can be omitted.
|
||||
For example:
|
||||
|
||||
For example, to map IOAPIC-ID decimal 10 to
|
||||
PCI segment 0x1 and PCI device 00:14.0,
|
||||
write the parameter as:
|
||||
ivrs_ioapic=10@0001:00:14.0
|
||||
|
||||
Deprecated formats:
|
||||
* To map IOAPIC-ID decimal 10 to PCI device 00:14.0
|
||||
write the parameter as:
|
||||
ivrs_ioapic[10]=00:14.0
|
||||
|
|
@ -2320,7 +2331,13 @@
|
|||
Provide an override to the HPET-ID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table.
|
||||
By default, PCI segment is 0, and can be omitted.
|
||||
For example:
|
||||
|
||||
For example, to map HPET-ID decimal 10 to
|
||||
PCI segment 0x1 and PCI device 00:14.0,
|
||||
write the parameter as:
|
||||
ivrs_hpet=10@0001:00:14.0
|
||||
|
||||
Deprecated formats:
|
||||
* To map HPET-ID decimal 0 to PCI device 00:14.0
|
||||
write the parameter as:
|
||||
ivrs_hpet[0]=00:14.0
|
||||
|
|
@ -2331,15 +2348,20 @@
|
|||
ivrs_acpihid [HW,X86-64]
|
||||
Provide an override to the ACPI-HID:UID<->DEVICE-ID
|
||||
mapping provided in the IVRS ACPI table.
|
||||
By default, PCI segment is 0, and can be omitted.
|
||||
|
||||
For example, to map UART-HID:UID AMD0020:0 to
|
||||
PCI segment 0x1 and PCI device ID 00:14.5,
|
||||
write the parameter as:
|
||||
ivrs_acpihid[0001:00:14.5]=AMD0020:0
|
||||
ivrs_acpihid=AMD0020:0@0001:00:14.5
|
||||
|
||||
By default, PCI segment is 0, and can be omitted.
|
||||
For example, PCI device 00:14.5 write the parameter as:
|
||||
Deprecated formats:
|
||||
* To map UART-HID:UID AMD0020:0 to PCI segment is 0,
|
||||
PCI device ID 00:14.5, write the parameter as:
|
||||
ivrs_acpihid[00:14.5]=AMD0020:0
|
||||
* To map UART-HID:UID AMD0020:0 to PCI segment 0x1 and
|
||||
PCI device ID 00:14.5, write the parameter as:
|
||||
ivrs_acpihid[0001:00:14.5]=AMD0020:0
|
||||
|
||||
js= [HW,JOY] Analog joystick
|
||||
See Documentation/input/joydev/joystick.rst.
|
||||
|
|
|
|||
|
|
@ -436,8 +436,8 @@ ignore-unaligned-usertrap
|
|||
|
||||
On architectures where unaligned accesses cause traps, and where this
|
||||
feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN``;
|
||||
currently, ``arc`` and ``ia64``), controls whether all unaligned traps
|
||||
are logged.
|
||||
currently, ``arc``, ``ia64`` and ``loongarch``), controls whether all
|
||||
unaligned traps are logged.
|
||||
|
||||
= =============================================================
|
||||
0 Log all unaligned accesses.
|
||||
|
|
@ -1492,8 +1492,8 @@ unaligned-trap
|
|||
|
||||
On architectures where unaligned accesses cause traps, and where this
|
||||
feature is supported (``CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW``; currently,
|
||||
``arc`` and ``parisc``), controls whether unaligned traps are caught
|
||||
and emulated (instead of failing).
|
||||
``arc``, ``parisc`` and ``loongarch``), controls whether unaligned traps
|
||||
are caught and emulated (instead of failing).
|
||||
|
||||
= ========================================================
|
||||
0 Do not emulate unaligned accesses.
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings
|
||||
title: Broadcom BCM2711/BCM2835 Platforms
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM11351 device tree bindings
|
||||
title: Broadcom BCM11351
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM21664 device tree bindings
|
||||
title: Broadcom BCM21664
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM23550 device tree bindings
|
||||
title: Broadcom BCM23550
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM4708 device tree bindings
|
||||
title: Broadcom BCM4708
|
||||
|
||||
description:
|
||||
Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Broadband SoC device tree bindings
|
||||
title: Broadcom Broadband SoC
|
||||
|
||||
description:
|
||||
Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Cygnus device tree bindings
|
||||
title: Broadcom Cygnus
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Hurricane 2 device tree bindings
|
||||
title: Broadcom Hurricane 2
|
||||
|
||||
description:
|
||||
Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom North Star 2 (NS2) device tree bindings
|
||||
title: Broadcom North Star 2 (NS2)
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Northstar Plus device tree bindings
|
||||
title: Broadcom Northstar Plus
|
||||
|
||||
description:
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray device tree bindings
|
||||
title: Broadcom Stingray
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Vulcan device tree bindings
|
||||
title: Broadcom Vulcan
|
||||
|
||||
maintainers:
|
||||
- Robert Richter <rrichter@marvell.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: CCI Interconnect Bus Masters binding
|
||||
title: CCI Interconnect Bus Masters
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/cpus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM CPUs bindings
|
||||
title: ARM CPUs
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: OP-TEE Device Tree Bindings
|
||||
title: OP-TEE
|
||||
|
||||
maintainers:
|
||||
- Jens Wiklander <jens.wiklander@linaro.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hisilicon Platforms Device Tree Bindings
|
||||
title: Hisilicon Platforms
|
||||
|
||||
maintainers:
|
||||
- Wei Xu <xuwei5@hisilicon.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common K3 TI-SCI bindings
|
||||
title: Common K3 TI-SCI
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI-SCI controller device node bindings
|
||||
title: TI-SCI controller
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 7K/8K Platforms Device Tree Bindings
|
||||
title: Marvell Armada 7K/8K Platforms
|
||||
|
||||
maintainers:
|
||||
- Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Platforms Device Tree Bindings
|
||||
title: Marvell Platforms
|
||||
|
||||
maintainers:
|
||||
- Lubomir Rintel <lkundrak@v3.sk>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar platforms device tree bindings
|
||||
title: MStar platforms
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NPCM Platforms Device Tree Bindings
|
||||
title: NPCM Platforms
|
||||
|
||||
maintainers:
|
||||
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/nxp/lpc32xx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP LPC32xx Platforms Device Tree Bindings
|
||||
title: NXP LPC32xx Platforms
|
||||
|
||||
maintainers:
|
||||
- Roland Stigge <stigge@antcom.de>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/socionext/milbeaut.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Milbeaut platforms device tree bindings
|
||||
title: Milbeaut platforms
|
||||
|
||||
maintainers:
|
||||
- Taichi Sugaya <sugaya.taichi@socionext.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier platform device tree bindings
|
||||
title: Socionext UniPhier platform
|
||||
|
||||
maintainers:
|
||||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/sp810.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express SP810 System Controller bindings
|
||||
title: ARM Versatile Express SP810 System Controller
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc platforms device tree bindings
|
||||
title: Unisoc platforms
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: STMicroelectronics STM32 ML-AHB interconnect bindings
|
||||
title: STMicroelectronics STM32 ML-AHB interconnect
|
||||
|
||||
maintainers:
|
||||
- Fabien Dessenne <fabien.dessenne@foss.st.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: STMicroelectronics STM32 Platforms System Controller bindings
|
||||
title: STMicroelectronics STM32 Platforms System Controller
|
||||
|
||||
maintainers:
|
||||
- Alexandre Torgue <alexandre.torgue@foss.st.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/stm32/stm32.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 Platforms Device Tree Bindings
|
||||
title: STMicroelectronics STM32 Platforms
|
||||
|
||||
maintainers:
|
||||
- Alexandre Torgue <alexandre.torgue@foss.st.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner CPU Configuration Controller Device Tree Bindings
|
||||
title: Allwinner CPU Configuration Controller
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun9i-a80-prcm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 PRCM Device Tree Bindings
|
||||
title: Allwinner A80 PRCM
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
|
||||
title: NVIDIA Tegra CPU COMPLEX CLUSTER area
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra194 CBB 1.0 bindings
|
||||
title: NVIDIA Tegra194 CBB 1.0
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra CBB 2.0 bindings
|
||||
title: NVIDIA Tegra CBB 2.0
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 Multicore SoC architecture device tree bindings
|
||||
title: Texas Instruments K3 Multicore SoC architecture
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/ti/ti,davinci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments DaVinci Platforms Device Tree Bindings
|
||||
title: Texas Instruments DaVinci Platforms
|
||||
|
||||
maintainers:
|
||||
- Sekhar Nori <nsekhar@ti.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express configuration bus bindings
|
||||
title: ARM Versatile Express configuration bus
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Versatile Express system registers bindings
|
||||
title: ARM Versatile Express system registers
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 AHCI SATA Controller bindings
|
||||
title: Allwinner A10 AHCI SATA Controller
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner R40 AHCI SATA Controller bindings
|
||||
title: Allwinner R40 AHCI SATA Controller
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments interconnect target module binding
|
||||
title: Texas Instruments interconnect target module
|
||||
|
||||
maintainers:
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for Analog Devices AXI clkgen pcore clock generator
|
||||
title: Analog Devices AXI clkgen pcore clock generator
|
||||
|
||||
maintainers:
|
||||
- Lars-Peter Clausen <lars@metafoo.de>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/calxeda.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Device Tree Clock bindings for Calxeda highbank platform
|
||||
title: Calxeda highbank platform Clock Controller
|
||||
|
||||
description: |
|
||||
This binding covers the Calxeda SoC internal peripheral and bus clocks
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
|
||||
title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
|
||||
|
||||
maintainers:
|
||||
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for simple fixed-rate clock sources
|
||||
title: Simple fixed-rate clock sources
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for simple fixed factor rate clock sources
|
||||
title: Simple fixed factor rate clock sources
|
||||
|
||||
maintainers:
|
||||
- Michael Turquette <mturquette@baylibre.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for simple memory mapped IO fixed-rate clock sources
|
||||
title: Simple memory mapped IO fixed-rate clock sources
|
||||
|
||||
description:
|
||||
This binding describes a fixed-rate clock for which the frequency can
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
|
||||
title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
|
||||
|
||||
maintainers:
|
||||
- Wen He <wen.he_1@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale SAI bitclock-as-a-clock binding
|
||||
title: Freescale SAI bitclock-as-a-clock
|
||||
|
||||
maintainers:
|
||||
- Michael Walle <michael@walle.cc>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol
|
||||
title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
|
||||
|
||||
maintainers:
|
||||
- Abel Vesa <abel.vesa@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
|
||||
title: IDT VersaClock 5 and 6 programmable I2C clock generators
|
||||
|
||||
description: |
|
||||
The IDT VersaClock 5 and VersaClock 6 are programmable I2C
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX1 CPUs
|
||||
title: Freescale i.MX1 CPUs Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Alexander Shiyan <shc_work@mail.ru>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX21
|
||||
title: Freescale i.MX21 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Alexander Shiyan <shc_work@mail.ru>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX23
|
||||
title: Freescale i.MX23 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX25
|
||||
title: Freescale i.MX25 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx27-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX27
|
||||
title: Freescale i.MX27 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX28
|
||||
title: Freescale i.MX28 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX31
|
||||
title: Freescale i.MX31 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX35
|
||||
title: Freescale i.MX35 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX5
|
||||
title: Freescale i.MX5 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 Quad
|
||||
title: Freescale i.MX6 Quad Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SoloLite
|
||||
title: Freescale i.MX6 SoloLite Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SLL
|
||||
title: Freescale i.MX6 SLL Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SoloX
|
||||
title: Freescale i.MX6 SoloX Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 UltraLite
|
||||
title: Freescale i.MX6 UltraLite Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX7 Dual
|
||||
title: Freescale i.MX7 Dual Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
|
||||
title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
|
||||
|
||||
maintainers:
|
||||
- A.s. Dong <aisheng.dong@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
|
||||
title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
|
||||
|
||||
maintainers:
|
||||
- A.s. Dong <aisheng.dong@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Family Clock Control Module Binding
|
||||
title: NXP i.MX8M Family Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
|
||||
title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
|
||||
|
||||
maintainers:
|
||||
- Aisheng Dong <aisheng.dong@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding
|
||||
title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
|
||||
|
||||
maintainers:
|
||||
- Jacky Bai <ping.bai@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
|
||||
title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
|
||||
|
||||
maintainers:
|
||||
- Jacky Bai <ping.bai@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX93 Clock Control Module Binding
|
||||
title: NXP i.MX93 Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MXRT
|
||||
title: Freescale i.MXRT Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ingenic SoCs CGU devicetree bindings
|
||||
title: Ingenic SoCs CGU
|
||||
|
||||
description: |
|
||||
The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA Agilex platform clock controller binding
|
||||
title: Intel SoCFPGA Agilex platform clock controller
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
|
||||
title: Intel Lightning Mountain SoC's Clock Controller(CGU)
|
||||
|
||||
maintainers:
|
||||
- Rahul Tanwar <rahul.tanwar@linux.intel.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA eASIC N5X platform clock controller binding
|
||||
title: Intel SoCFPGA eASIC N5X platform clock controller
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA Stratix10 platform clock controller binding
|
||||
title: Intel SoCFPGA Stratix10 platform clock controller
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire Clock Control Module Binding
|
||||
title: Microchip PolarFire Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Daire McNamara <daire.mcnamara@microchip.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Milbeaut SoCs Clock Controller Binding
|
||||
title: Milbeaut SoCs Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Taichi Sugaya <sugaya.taichi@socionext.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Nuvoton NPCM8XX Clock Controller Binding
|
||||
title: Nuvoton NPCM8XX Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Tomer Maimon <tmaimon77@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
|
||||
title: Qualcomm Display Clock & Reset Controller on SC8280XP
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Common Bindings
|
||||
title: Qualcomm Global Clock & Reset Controller Common Properties
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. RPMh Clocks Bindings
|
||||
title: Qualcomm Technologies, Inc. RPMh Clocks
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for Renesas 9-series I2C PCIe clock generators
|
||||
title: Renesas 9-series I2C PCIe clock generators
|
||||
|
||||
description: |
|
||||
The Renesas 9-series are I2C PCIe clock generators providing
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Versaclock7 Programmable Clock Device Tree Bindings
|
||||
title: Renesas Versaclock7 Programmable Clock
|
||||
|
||||
maintainers:
|
||||
- Alex Helms <alexander.helms.jy@renesas.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROCKCHIP rk3568 Family Clock Control Module Binding
|
||||
title: ROCKCHIP rk3568 Family Clock Control Module
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Reset Clock Controller Binding
|
||||
title: STMicroelectronics STM32MP1 Reset Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for the Texas Instruments LMK04832
|
||||
title: Texas Instruments LMK04832 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Liam Beguin <liambeguin@gmail.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI-SCI clock controller node bindings
|
||||
title: TI-SCI clock controller
|
||||
|
||||
maintainers:
|
||||
- Nishanth Menon <nm@ti.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for TI clksel clock
|
||||
title: TI clksel clock
|
||||
|
||||
maintainers:
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Idle states binding description
|
||||
title: Idle states
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek's CPUFREQ Bindings
|
||||
title: MediaTek's CPUFREQ
|
||||
|
||||
maintainers:
|
||||
- Hector Yuan <hector.yuan@mediatek.com>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
|
||||
title: Qualcomm Technologies, Inc. NVMEM CPUFreq
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRC bindings
|
||||
title: STMicroelectronics STM32 CRC
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@foss.st.com>
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user