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arm64: dts: qcom: lemans-evk: Enable 2.5G Ethernet interface

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Enable the QCA8081 2.5G Ethernet PHY on port 0. Add MDC and MDIO pin
functions for ethernet0, and enable the internal SGMII/SerDes PHY node.
Additionally, support fetching the MAC address from EEPROM via an nvmem
cell.

Signed-off-by: Mohd Ayaan Anwar <quic_mohdayaa@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-10-53d7d206669d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Mohd Ayaan Anwar 2025-09-16 16:16:58 +05:30 committed by Bjorn Andersson
parent c3f107b514
commit 71ee90ed17
1 changed files with 115 additions and 0 deletions
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115
arch/arm64/boot/dts/qcom/lemans-evk.dts
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@ -17,6 +17,7 @@ / {
compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
aliases {
ethernet0 = &ethernet0;
mmc1 = &sdhc;
serial0 = &uart10;
};
@ -352,6 +353,94 @@ vreg_l8e: ldo8 {
};
};
&ethernet0 {
phy-handle = <&hsgmii_phy0>;
phy-mode = "2500base-x";
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
nvmem-cells = <&mac_addr0>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy0: ethernet-phy@1c {
compatible = "ethernet-phy-id004d.d101";
reg = <0x1c>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&gpi_dma0 {
status = "okay";
};
@ -404,6 +493,10 @@ nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
mac_addr0: mac-addr@0 {
reg = <0x0 0x6>;
};
};
};
};
@ -552,11 +645,33 @@ &sdhc {
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32768>;
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
pcie0_default_state: pcie0-default-state {
clkreq-pins {
pins = "gpio1";