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drm/i915/display: Abstract pipe/trans/cursor offset calculation

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Introduce INTEL_DISPLAY_DEVICE_*_OFFSET() macros to compute absolute
MMIO offsets for pipe, transcoder, and cursor registers.

Update _MMIO_PIPE2/_MMIO_TRANS2/_MMIO_CURSOR2 to use these macros
for cleaner abstraction and to prepare for external API usage (e.g. GVT).

Also move DISPLAY_MMIO_BASE() to intel_display_device.h so it can be
abstracted in GVT, allowing register macros to resolve via
exported helpers rather than peeking into struct intel_display.

v2: Wrap the macro argument usages in parenthesis. (Jani)

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20251219060302.2365123-2-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2025-12-19 11:32:54 +05:30
parent fb48cb4355
commit 71813ecc84
2 changed files with 21 additions and 11 deletions
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17
drivers/gpu/drm/i915/display/intel_display_device.h
View File

@ -260,6 +260,23 @@ struct intel_display_platforms {
((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \
((id) == ARLS_HOST_BRIDGE_PCI_ID4))
#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \
(DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \
DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE((display)))
#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \
(DISPLAY_INFO((display))->trans_offsets[(trans)] - \
DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
DISPLAY_MMIO_BASE((display)))
#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \
(DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \
DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE((display)))
#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset)
struct intel_display_runtime_info {
struct intel_display_ip_ver {
u16 ver;

15
drivers/gpu/drm/i915/display/intel_display_reg_defs.h
View File

@ -8,8 +8,6 @@
#include "i915_reg_defs.h"
#define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
#define VLV_DISPLAY_BASE 0x180000
/*
@ -36,14 +34,9 @@
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
*/
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(display) + (reg))
#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
DISPLAY_MMIO_BASE(display) + (reg))
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(display) + (reg))
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg))
#define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg))
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg))
#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */