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arm64: dts: qcom: msm8996: Add PCIe bridge node

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On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2024-03-21 16:46:34 +05:30 committed by Bjorn Andersson
parent a92af45c40
commit 71756c44f1
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/qcom/msm8996.dtsi
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@ -1929,6 +1929,16 @@ pcie0: pcie@600000 {
"cfg",
"bus_master",
"bus_slave";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie1: pcie@608000 {
@ -1982,6 +1992,16 @@ pcie1: pcie@608000 {
"cfg",
"bus_master",
"bus_slave";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie2: pcie@610000 {
@ -2032,6 +2052,16 @@ pcie2: pcie@610000 {
"cfg",
"bus_master",
"bus_slave";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};