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drm/amdgpu: Add ras module ip block to amdgpu discovery
Add ras module ip block to amdgpu discovery. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -380,7 +380,7 @@ int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);
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int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
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int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
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#define AMDGPU_MAX_IP_NUM 16
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#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM
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struct amdgpu_ip_block_status {
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struct amdgpu_ip_block_status {
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bool valid;
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bool valid;
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@ -107,6 +107,7 @@
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#include "vcn_v5_0_1.h"
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#include "vcn_v5_0_1.h"
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#include "jpeg_v5_0_0.h"
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#include "jpeg_v5_0_0.h"
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#include "jpeg_v5_0_1.h"
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#include "jpeg_v5_0_1.h"
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#include "amdgpu_ras_mgr.h"
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#include "amdgpu_vpe.h"
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#include "amdgpu_vpe.h"
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#if defined(CONFIG_DRM_AMD_ISP)
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#if defined(CONFIG_DRM_AMD_ISP)
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@ -2393,6 +2394,21 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
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amdgpu_ip_version(adev, SDMA0_HWIP, 0));
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amdgpu_ip_version(adev, SDMA0_HWIP, 0));
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return -EINVAL;
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return -EINVAL;
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}
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}
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return 0;
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}
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static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)
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{
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switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
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case IP_VERSION(13, 0, 6):
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case IP_VERSION(13, 0, 12):
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case IP_VERSION(13, 0, 14):
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amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block);
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break;
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default:
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break;
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}
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return 0;
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return 0;
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}
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}
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@ -3173,6 +3189,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
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if (r)
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if (r)
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return r;
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return r;
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r = amdgpu_discovery_set_ras_ip_blocks(adev);
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if (r)
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return r;
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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!amdgpu_sriov_vf(adev)) ||
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!amdgpu_sriov_vf(adev)) ||
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(adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
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(adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
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@ -109,6 +109,7 @@ enum amd_ip_block_type {
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AMD_IP_BLOCK_TYPE_VPE,
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AMD_IP_BLOCK_TYPE_VPE,
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AMD_IP_BLOCK_TYPE_UMSCH_MM,
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AMD_IP_BLOCK_TYPE_UMSCH_MM,
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AMD_IP_BLOCK_TYPE_ISP,
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AMD_IP_BLOCK_TYPE_ISP,
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AMD_IP_BLOCK_TYPE_RAS,
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AMD_IP_BLOCK_TYPE_NUM,
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AMD_IP_BLOCK_TYPE_NUM,
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};
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};
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@ -381,6 +381,14 @@ static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = {
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.hw_fini = amdgpu_ras_mgr_hw_fini,
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.hw_fini = amdgpu_ras_mgr_hw_fini,
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};
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};
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const struct amdgpu_ip_block_version ras_v1_0_ip_block = {
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.type = AMD_IP_BLOCK_TYPE_RAS,
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.major = 1,
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.minor = 0,
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.rev = 0,
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.funcs = &ras_v1_0_ip_funcs,
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};
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int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable)
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int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable)
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{
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{
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struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
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struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
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@ -54,6 +54,8 @@ struct amdgpu_ras_mgr {
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bool ras_is_ready;
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bool ras_is_ready;
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};
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};
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extern const struct amdgpu_ip_block_version ras_v1_0_ip_block;
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struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(
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struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(
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struct amdgpu_device *adev);
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struct amdgpu_device *adev);
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int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);
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int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);
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