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clk: mstar: msc313-mpll: fix off-by-one in clock array allocation
The hws array of mpll->clk_data is allocated with struct_size() using
ARRAY_SIZE(output_dividers) as the element count, giving it 7 elements.
But the probe function stores the MPLL clock at hws[0] and one
fixed-factor clock for each output divider at hws[i + 1] for i in
[0, ARRAY_SIZE(output_dividers)), writing 8 elements in total. The
final write to hws[7] is past the end of the allocation.
clk_data->num is also set to NUMOUTPUTS (8), so the clock framework
reads hws[0..7], again accessing hws[7] out of bounds.
Use NUMOUTPUTS as the element count so the allocation matches the
number of clocks actually stored and exposed.
Found by smatch:
drivers/clk/mstar/clk-msc313-mpll.c:134 msc313_mpll_probe()
error: buffer overflow 'mpll->clk_data->hws' 7 <= 7
Fixes: bef7a78da7 ("clk: mstar: MStar/SigmaStar MPLL driver")
Cc: stable@vger.kernel.org
Signed-off-by: hanzhijian <hanzhijian1991@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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parent
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@ -105,7 +105,7 @@ static int msc313_mpll_probe(struct platform_device *pdev)
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return PTR_ERR(mpll->loop_div_second);
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mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,
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ARRAY_SIZE(output_dividers)), GFP_KERNEL);
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NUMOUTPUTS), GFP_KERNEL);
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if (!mpll->clk_data)
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return -ENOMEM;
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