From 7108abc25f3b6f97e3098650924816ccdbc06367 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Mon, 20 Jul 2026 22:12:16 +0800 Subject: [PATCH] arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET Change to use standard drive strength and slow slew rate on PTE14-17, 22, 23, otherwise the overshoot of ENET is too high. Signed-off-by: Wei Fang Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 9da54291c753..22c1d542798d 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -323,15 +323,15 @@ &mu { &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins = < - MX8ULP_PAD_PTE15__ENET0_MDC 0x43 - MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 - MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE15__ENET0_MDC 0x7 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x7 + MX8ULP_PAD_PTE17__ENET0_RXER 0x7 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 - MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 - MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 - MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x7 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x7 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x7 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >;