From 70f764ecca72bd35668b0c17426af4b088f4c88d Mon Sep 17 00:00:00 2001 From: "Mike Marciniszyn (Meta)" Date: Thu, 7 May 2026 11:42:03 -0400 Subject: [PATCH] net: eth: fbnic: Fix addr validation in pcs write The DW IP has two distinct PCS address ranges cooresponding to the C45 PCS registers. The shim translates the PCS addr/regno into specific CSR writes into one of those two zero-relative ranges. This patch fixes a one off in the test that could allow an invalid CSR write if an addr == 2 was called. There are is of yet, no real impact for the bug as no PCS writes are present. Signed-off-by: Mike Marciniszyn (Meta) Link: https://patch.msgid.link/20260507154203.3667-1-mike.marciniszyn@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/meta/fbnic/fbnic_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_mdio.c b/drivers/net/ethernet/meta/fbnic/fbnic_mdio.c index 7a8727e8f6f2..fe3a4ce88413 100644 --- a/drivers/net/ethernet/meta/fbnic/fbnic_mdio.c +++ b/drivers/net/ethernet/meta/fbnic/fbnic_mdio.c @@ -189,7 +189,7 @@ fbnic_mdio_write_pcs(struct fbnic_dev *fbd, int addr, int regnum, u16 val) addr, regnum, val); /* Allow access to both halves of PCS for 50R2 config */ - if (addr > 2) + if (addr >= 2) return; /* Skip write for reserved registers */