From 70d9feffcd30d0d8733bd5747bc1358176dc40b0 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 23 Mar 2017 15:31:26 +0100 Subject: [PATCH] net: phy: dp83867: Check if the phy is in an internal testing mode The DP83867 seems to be always in an internal mode on our Board. This mode can cause connection problems. We disable this mode. Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved. If Bit 7 is set, phy is in the internal testing mode. Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223 Signed-off-by: Wadim Egorov Signed-off-by: Jacob Chen --- drivers/net/phy/dp83867.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index a0028aa10a0f..01beabc31546 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -317,6 +317,16 @@ static int dp83867_config_init(struct phy_device *phydev) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); } + /* Check if the PHY is an internal testing mode. + * This mode can cause connection problems. + */ + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR); + if (val & BIT(7)) { + val &= ~BIT(7); + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, + val); + } + /* Disable FORCE_LINK_GOOD */ val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val & MII_DP83867_PHYCTRL_FORCE_LINK_GOOD) {