From 19e00bdfbb1b5f7a2d1f3c1c38b3da25e17ea486 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 8 Jun 2026 09:09:16 +0400 Subject: [PATCH 1/3] dt-bindings: net: ethernet-phy: increase max clock count to two The clocks property has a restriction to maximum one. Yet, some PHYs may require more than 1 clock such as the IPQ5018 PHY which requires two clocks for RX and TX. As such, increase maxItems to two. Reviewed-by: Rob Herring (Arm) Signed-off-by: George Moussalem Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-1-fb2ccd56894b@outlook.com Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 21a1a63506f0..c3ebb3af8b52 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -106,10 +106,13 @@ properties: by software. clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 description: - External clock connected to the PHY. If not specified it is assumed - that the PHY uses a fixed crystal or an internal oscillator. + External clock connected to the PHY or RX and TX clocks that the PHY + requires to enable explicitly. If not specified it is assumed + that the PHY uses a fixed crystal or an internal oscillator or that the + RX/TX clocks are hardware enabled by default. enet-phy-lane-swap: $ref: /schemas/types.yaml#/definitions/flag From fea4ae4b5b5059612d1a4f5acb88c27a5f7e60dc Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 8 Jun 2026 09:09:17 +0400 Subject: [PATCH 2/3] dt-bindings: net: qca,ar803x: Add clocks for IPQ5018 PHY Further testing revealed that the RX and TX clocks of the IPQ5018 PHY need to be explicitly enabled. As such, add the required clocks to the schema. Acked-by: Conor Dooley Signed-off-by: George Moussalem Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-2-fb2ccd56894b@outlook.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/qca,ar803x.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 7ae5110e7aa2..53f648c4135f 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -28,6 +28,16 @@ allOf: reg: const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC + clocks: + items: + - description: RX clock + - description: TX clock + + clock-names: + items: + - const: rx + - const: tx + resets: items: - description: @@ -42,6 +52,11 @@ allOf: of this PHY are directly connected to an RJ45 connector. type: boolean + required: + - clocks + - clock-names + - resets + properties: compatible: enum: @@ -162,6 +177,7 @@ examples: }; }; - | + #include #include mdio { @@ -172,6 +188,9 @@ examples: compatible = "ethernet-phy-id004d.d0c0"; reg = <7>; + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + clock-names = "rx", "tx"; resets = <&gcc GCC_GEPHY_MISC_ARES>; }; }; From cf6077e4903ffed2291f5f3cb9d61b29abe456c4 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 8 Jun 2026 09:09:19 +0400 Subject: [PATCH 3/3] net: phy: at803x: add RX and TX clock management for IPQ5018 PHY Acquire and enable the RX and TX clocks for the IPQ5018 PHY. These clocks are required for the PHY's datapath to function correctly. Signed-off-by: George Moussalem Link: https://patch.msgid.link/20260608-ipq5018-gephy-clocks-v4-4-fb2ccd56894b@outlook.com Signed-off-by: Jakub Kicinski --- drivers/net/phy/qcom/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 63726cf98cd4..ba4dc07752b6 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1074,6 +1075,7 @@ static void ipq5018_link_change_notify(struct phy_device *phydev) static int ipq5018_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; + struct clk *rx_clk, *tx_clk; struct ipq5018_priv *priv; int ret; @@ -1084,6 +1086,16 @@ static int ipq5018_probe(struct phy_device *phydev) priv->set_short_cable_dac = of_property_read_bool(dev->of_node, "qcom,dac-preset-short-cable"); + rx_clk = devm_clk_get_enabled(dev, "rx"); + if (IS_ERR(rx_clk)) + return dev_err_probe(dev, PTR_ERR(rx_clk), + "failed to get and enable RX clock\n"); + + tx_clk = devm_clk_get_enabled(dev, "tx"); + if (IS_ERR(tx_clk)) + return dev_err_probe(dev, PTR_ERR(tx_clk), + "failed to get and enable TX clock\n"); + priv->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(priv->rst)) return dev_err_probe(dev, PTR_ERR(priv->rst),