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arm64: dts: rockchip: Add naneng-combphy for RK3528

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Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
3.0 controllers. Describe it and the pipe-phy grf which it depends on.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250728102947.38984-8-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Yao Zi 2025-07-28 10:29:48 +00:00 committed by Heiko Stuebner
parent 1bce3444df
commit 70bb21cbc8
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@ -417,6 +417,11 @@ vpu_grf: syscon@ff340000 {
reg = <0x0 0xff340000 0x0 0x8000>;
};
pipe_phy_grf: syscon@ff348000 {
compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
reg = <0x0 0xff348000 0x0 0x8000>;
};
vo_grf: syscon@ff360000 {
compatible = "rockchip,rk3528-vo-grf", "syscon";
reg = <0x0 0xff360000 0x0 0x10000>;
@ -1085,6 +1090,25 @@ dmac: dma-controller@ffd60000 {
#dma-cells = <1>;
arm,pl330-periph-burst;
};
combphy: phy@ffdc0000 {
compatible = "rockchip,rk3528-naneng-combphy";
reg = <0x0 0xffdc0000 0x0 0x10000>;
assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
assigned-clock-rates = <100000000>;
clocks = <&cru CLK_REF_PCIE_INNER_PHY>,
<&cru PCLK_PCIE_PHY>,
<&cru PCLK_PIPE_GRF>;
clock-names = "ref", "apb", "pipe";
power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_PCIE_PIPE_PHY>,
<&cru SRST_P_PCIE_PHY>;
reset-names = "phy", "apb";
#phy-cells = <1>;
rockchip,pipe-grf = <&vpu_grf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf>;
status = "disabled";
};
};
};