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soc: qcom: ubwc: Add #defines for UBWC swizzle bits

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Make the values a bit more meaningful.

This commit is intentionally cross-subsystem to ease review, as the
patchset is intended to be merged together, with a maintainer
consensus.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660981/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Konrad Dybcio 2025-06-26 11:02:39 +02:00 committed by Rob Clark
parent caf5ad18a2
commit 709dd2ff23
3 changed files with 30 additions and 17 deletions
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2
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -680,7 +680,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2);
bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
bool min_acc_len_64b = false;

37
drivers/soc/qcom/ubwc_config.c
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@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {
static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 4,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 13,
.macrotile_mode = true,
@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
static const struct qcom_ubwc_cfg_data sar2130p_data = {
.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
.ubwc_dec_version = UBWC_4_3,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 13,
.macrotile_mode = true,
@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
static const struct qcom_ubwc_cfg_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data = {
static const struct qcom_ubwc_cfg_data sc7280_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
.macrotile_mode = true,
@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
static const struct qcom_ubwc_cfg_data sc8280xp_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 16,
.macrotile_mode = true,
@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data = {
static const struct qcom_ubwc_cfg_data sm6115_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 7,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
static const struct qcom_ubwc_cfg_data sm6125_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_3_0,
.ubwc_swizzle = 7,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.highest_bank_bit = 14,
};
@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
static const struct qcom_ubwc_cfg_data sm6350_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {
static const struct qcom_ubwc_cfg_data sm8250_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
static const struct qcom_ubwc_cfg_data sm8350_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
static const struct qcom_ubwc_cfg_data sm8550_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_3,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data = {
static const struct qcom_ubwc_cfg_data x1e80100_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_3,
.ubwc_swizzle = 6,
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,

8
include/linux/soc/qcom/ubwc.h
View File

@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data {
* UBWC 1.0 always enables all three levels.
* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
*
* This is a bitmask where BIT(0) enables level 1, BIT(1)
* controls level 2, and BIT(2) enables level 3.
*/
u32 ubwc_swizzle;
#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
/**
* @highest_bank_bit: Highest Bank Bit
@ -66,7 +66,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
{
bool ret = cfg->ubwc_enc_version == UBWC_1_0;
if (ret && !(cfg->ubwc_swizzle & BIT(0)))
if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
return ret;