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Merge branch 'pci/dt-bindings'

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- Add "apb", "sys", "pmc", "msg", "err" for Endpoint descriptions as well
  as for Root Complexes (Niklas Cassel)

- Add "tx_inta", "tx_intb", "tx_intc", "tx_intd" for interrupt signals
  triggered in response to PCIe Assert_INTx messages (Niklas Cassel)

- Refactor rockchip-dw-pcie binding to move generic properties to a new
  rockchip-dw-pcie-common binding that can be shared by both RC and EP mode
  (Niklas Cassel)

- Fix rockchip-dw-pcie description of INTx signals (Niklas Cassel)

- Add rockchip-dw-pcie description of Endpoint controller (Niklas Cassel)

- Avoid xilinx-versal-cpm overlapping of bridge registers and 32-bit BAR
  addresses (Thippeswamy Havalige)

- Add qcom Operating Performance Points (OPP) table (Krishna chaitanya
  chundru)

- Add a picture of mediatek,mt7621-pcie topology (Sergio Paracuellos)

- Add a generic "ats-supported" property so the OS can discover whether a
  Root Complex supports ATS (Jean-Philippe Brucker)

- Make the qcom,pcie-x1e80100 MHI register region mandatory (Abel Vesa)

* pci/dt-bindings:
  dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory
  dt-bindings: PCI: generic: Add ats-supported property
  dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graph
  dt-bindings: PCI: qcom: Add OPP table
  dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit BAR addresses
  dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller
  dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ
  dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
  dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs
  dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
  dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
This commit is contained in:
Bjorn Helgaas 2024-07-19 10:10:24 -05:00
commit 7095d21ef5
9 changed files with 276 additions and 95 deletions
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6
Documentation/devicetree/bindings/pci/host-generic-pci.yaml
View File

@ -110,6 +110,12 @@ properties:
iommu-map-mask: true
msi-parent: true
ats-supported:
description:
Indicates that a PCIe host controller supports ATS, and can handle Memory
Requests with Address Type (AT).
type: boolean
required:
- compatible
- reg

29
Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
View File

@ -13,6 +13,35 @@ description: |+
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
MT7621 PCIe HOST Topology
.-------.
| |
| CPU |
| |
'-------'
|
|
|
v
.------------------.
.-----------| HOST/PCI Bridge |------------.
| '------------------' | Type1
BUS0 | | | Access
v v v On Bus0
.-------------. .-------------. .-------------.
| VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
| BUS0 | | BUS0 | | BUS0 |
| DEV0 | | DEV1 | | DEV2 |
'-------------' '-------------' '-------------'
Type0 | Type0 | Type0 |
Access BUS1 | Access BUS2| Access BUS3|
On Bus1 v On Bus2 v On Bus3 v
.----------. .----------. .----------.
| Device 0 | | Device 0 | | Device 0 |
| Func 0 | | Func 0 | | Func 0 |
'----------' '----------' '----------'
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#

4
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
View File

@ -69,6 +69,10 @@ properties:
- const: msi6
- const: msi7
operating-points-v2: true
opp-table:
type: object
resets:
maxItems: 1

3
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
View File

@ -19,11 +19,10 @@ properties:
const: qcom,pcie-x1e80100
reg:
minItems: 5
minItems: 6
maxItems: 6
reg-names:
minItems: 5
items:
- const: parf # Qualcomm specific registers
- const: dbi # DesignWare PCIe registers

126
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml Normal file
View File

@ -0,0 +1,126 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
- Simon Xue <xxm@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |+
Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
SoCs.
properties:
clocks:
minItems: 5
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
- description: PIPE clock
- description: Reference clock for PCIe
clock-names:
minItems: 5
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
- const: pipe
- const: ref
interrupts:
minItems: 5
items:
- description:
Combined system interrupt, which is used to signal the following
interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
- description:
Combined PM interrupt, which is used to signal the following
interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
linkst_out_l0s, pm_dstate_update
- description:
Combined message interrupt, which is used to signal the following
interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- description:
Combined legacy interrupt, which is used to signal the following
interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
tx_intd
- description:
Combined error interrupt, which is used to signal the following
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
- description:
eDMA write channel 0 interrupt
- description:
eDMA write channel 1 interrupt
- description:
eDMA read channel 0 interrupt
- description:
eDMA read channel 1 interrupt
interrupt-names:
minItems: 5
items:
- const: sys
- const: pmc
- const: msg
- const: legacy
- const: err
- const: dma0
- const: dma1
- const: dma2
- const: dma3
num-lanes: true
phys:
maxItems: 1
phy-names:
const: pcie-phy
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 2
reset-names:
oneOf:
- const: pipe
- items:
- const: pwr
- const: pipe
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- num-lanes
- phys
- phy-names
- power-domains
- resets
- reset-names
additionalProperties: true
...

95
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml Normal file
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@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
maintainers:
- Niklas Cassel <cassel@kernel.org>
description: |+
RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie-ep.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
properties:
compatible:
enum:
- rockchip,rk3568-pcie-ep
- rockchip,rk3588-pcie-ep
reg:
items:
- description: Data Bus Interface (DBI) registers
- description: Data Bus Interface (DBI) shadow registers
- description: Rockchip designed configuration registers
- description: Memory region used to map remote RC address space
- description: Internal Address Translation Unit (iATU) registers
reg-names:
items:
- const: dbi
- const: dbi2
- const: apb
- const: addr_space
- const: atu
required:
- interrupts
- interrupt-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie3x4_ep: pcie-ep@fe150000 {
compatible = "rockchip,rk3588-pcie-ep";
reg = <0xa 0x40000000 0x0 0x00100000>,
<0xa 0x40100000 0x0 0x00100000>,
<0x0 0xfe150000 0x0 0x00010000>,
<0x9 0x00000000 0x0 0x40000000>,
<0xa 0x40300000 0x0 0x00100000>;
reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err",
"dma0", "dma1", "dma2", "dma3";
max-link-speed = <3>;
num-lanes = <4>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pwr", "pipe";
};
};
...

93
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
View File

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DesignWare based PCIe controller on Rockchip SoCs
title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
@ -12,12 +12,13 @@ maintainers:
- Heiko Stuebner <heiko@sntech.de>
description: |+
RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
properties:
compatible:
@ -40,61 +41,6 @@ properties:
- const: apb
- const: config
clocks:
minItems: 5
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
- description: PIPE clock
- description: Reference clock for PCIe
clock-names:
minItems: 5
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
- const: pipe
- const: ref
interrupts:
items:
- description:
Combined system interrupt, which is used to signal the following
interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
- description:
Combined PM interrupt, which is used to signal the following
interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
linkst_out_l0s, pm_dstate_update
- description:
Combined message interrupt, which is used to signal the following
interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- description:
Combined legacy interrupt, which is used to signal the following
interrupts - inta, intb, intc, intd
- description:
Combined error interrupt, which is used to signal the following
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
interrupt-names:
items:
- const: sys
- const: pmc
- const: msg
- const: legacy
- const: err
legacy-interrupt-controller:
description: Interrupt controller node for handling legacy PCI interrupts.
type: object
@ -119,47 +65,14 @@ properties:
msi-map: true
num-lanes: true
phys:
maxItems: 1
phy-names:
const: pcie-phy
power-domains:
maxItems: 1
ranges:
minItems: 2
maxItems: 3
resets:
minItems: 1
maxItems: 2
reset-names:
oneOf:
- const: pipe
- items:
- const: pwr
- const: pipe
vpcie3v3-supply: true
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- msi-map
- num-lanes
- phys
- phy-names
- power-domains
- resets
- reset-names
unevaluatedProperties: false

13
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
View File

@ -100,7 +100,7 @@ properties:
for new bindings.
oneOf:
- description: See native 'elbi/app' CSR region for details.
enum: [ link, appl ]
enum: [ apb, link, appl ]
- description: See native 'atu' CSR region for details.
enum: [ atu_dma ]
allOf:
@ -151,12 +151,21 @@ properties:
Application-specific IRQ raised depending on the vendor-specific
events basis.
const: app
- description:
Interrupts triggered when the controller itself (in Endpoint mode)
has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to
the upstream device.
pattern: "^tx_int(a|b|c|d)$"
- description:
Combined interrupt signal raised when the controller has sent an
Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details.
const: legacy
- description:
Vendor-specific IRQ names. Consider using the generic names above
for new bindings.
oneOf:
- description: See native "app" IRQ for details
enum: [ intr ]
enum: [ intr, sys, pmc, msg, err ]
max-functions:
maximum: 32

2
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
View File

@ -92,7 +92,7 @@ examples:
<0 0 0 3 &pcie_intc_0 2>,
<0 0 0 4 &pcie_intc_0 3>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x0 0xfca10000 0x0 0x1000>,