From 707ec089ca32a9e69da448a37b8c2ad3248e0457 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Mon, 21 May 2018 16:13:54 +0800 Subject: [PATCH] BACKPORT: FROMLIST: soc: rockchip: split rockchip_typec_phy struct to separate header we may use rockchip_phy_typec struct in other driver, so split it to separate header. Signed-off-by: Lin Huang (am from https://patchwork.kernel.org/patch/10420467/) Conflicts: drivers/phy/phy-rockchip-typec.c [phy-rockchip-typec.c is different path in upstream code] BUG=b:72006974 TEST=DP display on Dru Signed-off-by: Lin Huang Signed-off-by: Brian Norris Reviewed-on: https://chromium-review.googlesource.com/1069958 Change-Id: I709331d1577923be662660eb606f92b743903ba7 Signed-off-by: Wyon Bi --- drivers/phy/rockchip/phy-rockchip-typec.c | 35 +----------------- include/soc/rockchip/rockchip_phy_typec.h | 44 +++++++++++++++++++++++ 2 files changed, 45 insertions(+), 34 deletions(-) create mode 100644 include/soc/rockchip/rockchip_phy_typec.h diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 133a790163c1..bcc635a6b3a4 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -63,6 +63,7 @@ #include #include +#include #define CMN_SSM_BANDGAP (0x21 << 2) #define CMN_SSM_BIAS (0x22 << 2) @@ -351,40 +352,6 @@ #define POWER_ON_TRIES 5 -struct usb3phy_reg { - u32 offset; - u32 enable_bit; - u32 write_enable; -}; - -struct rockchip_usb3phy_port_cfg { - struct usb3phy_reg typec_conn_dir; - struct usb3phy_reg usb3tousb2_en; - struct usb3phy_reg usb3host_disable; - struct usb3phy_reg usb3host_port; - struct usb3phy_reg external_psm; - struct usb3phy_reg pipe_status; - struct usb3phy_reg uphy_dp_sel; -}; - -struct rockchip_typec_phy { - struct device *dev; - void __iomem *base; - struct extcon_dev *extcon; - struct regmap *grf_regs; - struct clk *clk_core; - struct clk *clk_ref; - struct reset_control *uphy_rst; - struct reset_control *pipe_rst; - struct reset_control *tcphy_rst; - struct rockchip_usb3phy_port_cfg port_cfgs; - /* mutex to protect access to individual PHYs */ - struct mutex lock; - - bool flip; - u8 mode; -}; - struct phy_reg { u16 value; u32 addr; diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h new file mode 100644 index 000000000000..b13d01368b76 --- /dev/null +++ b/include/soc/rockchip/rockchip_phy_typec.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Lin Huang + */ + +#ifndef __SOC_ROCKCHIP_PHY_TYPEC_H +#define __SOC_ROCKCHIP_PHY_TYPEC_H + +struct usb3phy_reg { + u32 offset; + u32 enable_bit; + u32 write_enable; +}; + +struct rockchip_usb3phy_port_cfg { + struct usb3phy_reg typec_conn_dir; + struct usb3phy_reg usb3tousb2_en; + struct usb3phy_reg usb3host_disable; + struct usb3phy_reg usb3host_port; + struct usb3phy_reg external_psm; + struct usb3phy_reg pipe_status; + struct usb3phy_reg uphy_dp_sel; +}; + +struct rockchip_typec_phy { + struct device *dev; + void __iomem *base; + struct extcon_dev *extcon; + struct regmap *grf_regs; + struct clk *clk_core; + struct clk *clk_ref; + struct reset_control *uphy_rst; + struct reset_control *pipe_rst; + struct reset_control *tcphy_rst; + struct rockchip_usb3phy_port_cfg port_cfgs; + /* mutex to protect access to individual PHYs */ + struct mutex lock; + + bool flip; + u8 mode; +}; + +#endif