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wifi: rtw89: phy: add BB wrapper generation 3 for RTL8922D variant

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The BB wrapper generation 3 support more settings to fine tune power
threshold and CCK CFIR/filter per RFSI band. Add them accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260511070148.25257-12-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2026-05-11 15:01:48 +08:00
parent 4f2b5c8365
commit 7076af6429
4 changed files with 212 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/net/wireless/realtek/rtw89/phy.h
View File

@ -603,6 +603,16 @@ enum rtw89_rfsi_ctrl_modulation {
RFSI_MAX,
};
enum rtw89_cfir_onoff {
CFIR_ON = 1,
CFIR_OFF = 0,
};
enum rtw89_filter_onoff {
FILTER_A_ON = 1,
FILTER_A_OFF = 0,
};
#define MAX_TX_RFSI_CTRL_OPT 10
#define _8nibble(n0, n1, n2, n3, n4, n5, n6, n7) \
@ -629,8 +639,16 @@ struct rtw89_bb_wrap_common_data {
u8 qam_th[6];
};
struct rtw89_bb_wrap_common_data_gen3 {
struct {
u8 qam_th[6];
} bands[RFSI_CTRL_BAND_NUM];
u8 cck_val[2];
};
struct rtw89_bb_wrap_data {
const struct rtw89_bb_wrap_common_data *common;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
struct {
u16 qam_comp_th0[MAX_TX_RFSI_CTRL_OPT];
u16 qam_comp_th1[MAX_TX_RFSI_CTRL_OPT]; /* encoded */

112
drivers/net/wireless/realtek/rtw89/phy_be.c
View File

@ -769,6 +769,75 @@ static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev,
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, 0x2, mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
const u8 *ths;
if (!d || !d->common_gen3)
return;
common_gen3 = d->common_gen3;
ths = common_gen3->bands[chan->rfsi_band].qam_th;
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_0_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_1_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_2_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_3_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_4_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_5_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_6_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH0_7_BE4, ths[0], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_0_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH0_BE4, B_QAM3_TH1_1_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_2_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_3_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_4_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_5_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_6_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH1_7_BE4, ths[1], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_0_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_1_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_2_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH1_BE4, B_QAM3_TH2_3_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_4_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_5_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_6_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH2_7_BE4, ths[2], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_0_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_1_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_2_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_3_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_4_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH2_BE4, B_QAM3_TH3_5_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_6_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH3_7_BE4, ths[3], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_0_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_1_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_2_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_3_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_4_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_5_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_6_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_TH4_7_BE4, ths[4], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_0_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_1_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_2_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_3_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_4_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_5_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_6_BE4, ths[5], mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH3_BE4, B_QAM3_TH5_7_BE4, ths[5], mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
@ -987,6 +1056,39 @@ static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev,
rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_VAL, 0, mac_idx);
}
static void rtw89_phy_bb_set_cck_cfir_filter_val_gen3(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
u8 cck0, cck1;
if (!d || !d->common_gen3)
return;
common_gen3 = d->common_gen3;
cck0 = common_gen3->cck_val[0];
cck1 = common_gen3->cck_val[1];
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR0_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR1_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR2_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR3_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR4_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR5_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR6_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_TH4_BE4, B_QAM3_CFIR7_BE4, cck0, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR0_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR1_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR2_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR3_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR4_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR5_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR6_BE4, cck1, mac_idx);
rtw89_write32_idx(rtwdev, R_QAM3_FLTR_BE4, B_QAM3_FLTR7_BE4, cck1, mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
@ -998,18 +1100,18 @@ static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,
if (chip_id != RTL8922D)
return;
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[phy_idx];
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_gen3_init(rtwdev, chan, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, mac_idx);
rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx);
rtw89_phy_bb_set_cim3k_val(rtwdev, mac_idx);
rtw89_phy_bb_set_cck_cfir_filter_val_gen3(rtwdev, mac_idx);
rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, 0, phy_idx);
rtw89_entity_get_conf(rtwdev, &conf);
chan = conf.chans[phy_idx];
rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx);
}

70
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -10599,6 +10599,17 @@
#define R_CIM3K_SU_FORCE 0x119F8
#define B_CIM3K_SU_FORCE_EN BIT(17)
#define B_CIM3K_SU_FORCE_VAL BIT(18)
#define R_QAM3_TH0_BE4 0x119FC
#define B_QAM3_TH0_0_BE4 GENMASK(2, 0)
#define B_QAM3_TH0_1_BE4 GENMASK(5, 3)
#define B_QAM3_TH0_2_BE4 GENMASK(8, 6)
#define B_QAM3_TH0_3_BE4 GENMASK(11, 9)
#define B_QAM3_TH0_4_BE4 GENMASK(14, 12)
#define B_QAM3_TH0_5_BE4 GENMASK(17, 15)
#define B_QAM3_TH0_6_BE4 GENMASK(20, 18)
#define B_QAM3_TH0_7_BE4 GENMASK(23, 21)
#define B_QAM3_TH1_0_BE4 GENMASK(26, 24)
#define B_QAM3_TH1_1_BE4 GENMASK(29, 27)
#define R_RFSI_CT_OPT_0_BE4 0x11A94
#define R_RFSI_CT_OPT_8_BE4 0x11A98
#define R_QAM_COMP_TH0_BE4 0x11A9C
@ -10634,6 +10645,65 @@
#define B_BANDEDGE_DBW80_BE4 BIT(31)
#define R_BANDEDGE_DBWY_BE4 0x11AD0
#define B_BANDEDGE_DBW160_BE4 BIT(0)
#define R_QAM3_TH1_BE4 0x11BE8
#define B_QAM3_TH1_2_BE4 GENMASK(2, 0)
#define B_QAM3_TH1_3_BE4 GENMASK(5, 3)
#define B_QAM3_TH1_4_BE4 GENMASK(8, 6)
#define B_QAM3_TH1_5_BE4 GENMASK(11, 9)
#define B_QAM3_TH1_6_BE4 GENMASK(14, 12)
#define B_QAM3_TH1_7_BE4 GENMASK(17, 15)
#define B_QAM3_TH2_0_BE4 GENMASK(20, 18)
#define B_QAM3_TH2_1_BE4 GENMASK(23, 21)
#define B_QAM3_TH2_2_BE4 GENMASK(26, 24)
#define B_QAM3_TH2_3_BE4 GENMASK(29, 27)
#define R_QAM3_TH2_BE4 0x11BEC
#define B_QAM3_TH2_4_BE4 GENMASK(2, 0)
#define B_QAM3_TH2_5_BE4 GENMASK(5, 3)
#define B_QAM3_TH2_6_BE4 GENMASK(8, 6)
#define B_QAM3_TH2_7_BE4 GENMASK(11, 9)
#define B_QAM3_TH3_0_BE4 GENMASK(14, 12)
#define B_QAM3_TH3_1_BE4 GENMASK(17, 15)
#define B_QAM3_TH3_2_BE4 GENMASK(20, 18)
#define B_QAM3_TH3_3_BE4 GENMASK(23, 21)
#define B_QAM3_TH3_4_BE4 GENMASK(26, 24)
#define B_QAM3_TH3_5_BE4 GENMASK(29, 27)
#define R_QAM3_TH3_BE4 0x11BF4
#define B_QAM3_TH3_6_BE4 GENMASK(2, 0)
#define B_QAM3_TH3_7_BE4 GENMASK(5, 3)
#define B_QAM3_TH5_0_BE4 GENMASK(8, 6)
#define B_QAM3_TH5_1_BE4 GENMASK(11, 9)
#define B_QAM3_TH5_2_BE4 GENMASK(14, 12)
#define B_QAM3_TH5_3_BE4 GENMASK(17, 15)
#define B_QAM3_TH5_4_BE4 GENMASK(20, 18)
#define B_QAM3_TH5_5_BE4 GENMASK(23, 21)
#define B_QAM3_TH5_6_BE4 GENMASK(26, 24)
#define B_QAM3_TH5_7_BE4 GENMASK(29, 27)
#define R_QAM3_TH4_BE4 0x11BF8
#define B_QAM3_TH4_0_BE4 GENMASK(2, 0)
#define B_QAM3_TH4_1_BE4 GENMASK(5, 3)
#define B_QAM3_TH4_2_BE4 GENMASK(8, 6)
#define B_QAM3_TH4_3_BE4 GENMASK(11, 9)
#define B_QAM3_TH4_4_BE4 GENMASK(14, 12)
#define B_QAM3_TH4_5_BE4 GENMASK(17, 15)
#define B_QAM3_TH4_6_BE4 GENMASK(20, 18)
#define B_QAM3_TH4_7_BE4 GENMASK(23, 21)
#define B_QAM3_CFIR0_BE4 BIT(24)
#define B_QAM3_CFIR1_BE4 BIT(25)
#define B_QAM3_CFIR2_BE4 BIT(26)
#define B_QAM3_CFIR3_BE4 BIT(27)
#define B_QAM3_CFIR4_BE4 BIT(28)
#define B_QAM3_CFIR5_BE4 BIT(29)
#define B_QAM3_CFIR6_BE4 BIT(30)
#define B_QAM3_CFIR7_BE4 BIT(31)
#define R_QAM3_FLTR_BE4 0x11BFC
#define B_QAM3_FLTR0_BE4 GENMASK(1, 0)
#define B_QAM3_FLTR1_BE4 GENMASK(3, 2)
#define B_QAM3_FLTR2_BE4 GENMASK(5, 4)
#define B_QAM3_FLTR3_BE4 GENMASK(7, 6)
#define B_QAM3_FLTR4_BE4 GENMASK(9, 8)
#define B_QAM3_FLTR5_BE4 GENMASK(11, 10)
#define B_QAM3_FLTR6_BE4 GENMASK(13, 12)
#define B_QAM3_FLTR7_BE4 GENMASK(15, 14)
#define R_SYS_DBCC_BE4 0x20000
#define B_SYS_DBCC_BE4 BIT(0)

17
drivers/net/wireless/realtek/rtw89/rtw8922d.c
View File

@ -320,8 +320,23 @@ static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7090
.qam_th = {RFSI_BPSK, RFSI_QPSK, RFSI_256QAM, RFSI_MAX, RFSI_MAX, RFSI_MAX},
};
static const
struct rtw89_bb_wrap_common_data_gen3 rtw8922d_bb_wrap_common_data_gen3_7090 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_th = {RFSI_QPSK, RFSI_BPSK, RFSI_256QAM, RFSI_MAX,
RFSI_MAX, RFSI_MAX},
},
[RFSI_CTRL_BAND_2GHZ] = {
.qam_th = {RFSI_MAX, RFSI_MAX, RFSI_256QAM, RFSI_MAX,
RFSI_MAX, RFSI_MAX},
}},
.cck_val = {CFIR_OFF, FILTER_A_OFF},
};
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7025_default = {
.common = &rtw8922d_bb_wrap_common_data_7025,
.common_gen3 = NULL,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6400, 0x6500, 0x6000, 0, 0, 0, 0, 0, 0},
@ -348,6 +363,7 @@ static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7025_default = {
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_default = {
.common = &rtw8922d_bb_wrap_common_data_7090,
.common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},
@ -374,6 +390,7 @@ static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_default = {
static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_rfe35_41_44 = {
.common = &rtw8922d_bb_wrap_common_data_7090,
.common_gen3 = &rtw8922d_bb_wrap_common_data_gen3_7090,
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.qam_comp_th0 = {0x4000, 0x6420, 0x6520, 0x6000, 0, 0, 0, 0, 0, 0},