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drm/i915/fb: move user framebuffer stuff to intel_fb.c
Split out fb related stuff from intel_display.c to intel_fb.c. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/76b61738857619c1cce6e4306d14da19ee3bbf08.1629721467.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
1c8d9adfc3
commit
705d4feeb2
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@ -112,9 +112,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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static void ilk_pch_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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static int intel_framebuffer_init(struct intel_framebuffer *ifb,
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struct drm_i915_gem_object *obj,
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struct drm_mode_fb_cmd2 *mode_cmd);
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static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
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static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
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static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
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@ -1134,22 +1131,6 @@ void intel_add_fb_offsets(int *x, int *y,
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*y += state->view.color_plane[color_plane].y;
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}
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static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
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{
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switch (fb_modifier) {
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case I915_FORMAT_MOD_X_TILED:
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return I915_TILING_X;
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_Y_TILED_CCS:
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case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
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case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
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case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
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return I915_TILING_Y;
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default:
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return I915_TILING_NONE;
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}
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}
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/*
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* From the Sky Lake PRM:
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* "The Color Control Surface (CCS) contains the compression status of
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@ -1280,12 +1261,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
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}
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}
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static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
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{
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return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
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512) * 64;
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}
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u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
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u32 pixel_format, u64 modifier)
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{
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@ -1310,71 +1285,6 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
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DRM_MODE_ROTATE_0);
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}
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static
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u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
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u32 pixel_format, u64 modifier)
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{
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/*
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* Arbitrary limit for gen4+ chosen to match the
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* render engine max stride.
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*
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* The new CCS hash mode makes remapping impossible
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*/
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if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
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intel_modifier_uses_dpt(dev_priv, modifier))
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return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
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else if (DISPLAY_VER(dev_priv) >= 7)
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return 256 * 1024;
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else
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return 128 * 1024;
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}
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static u32
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intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
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{
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struct drm_i915_private *dev_priv = to_i915(fb->dev);
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u32 tile_width;
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if (is_surface_linear(fb, color_plane)) {
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u32 max_stride = intel_plane_fb_max_stride(dev_priv,
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fb->format->format,
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fb->modifier);
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/*
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* To make remapping with linear generally feasible
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* we need the stride to be page aligned.
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*/
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if (fb->pitches[color_plane] > max_stride &&
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!is_ccs_modifier(fb->modifier))
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return intel_tile_size(dev_priv);
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else
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return 64;
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}
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tile_width = intel_tile_width_bytes(fb, color_plane);
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if (is_ccs_modifier(fb->modifier)) {
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/*
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* Display WA #0531: skl,bxt,kbl,glk
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*
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* Render decompression and plane width > 3840
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* combined with horizontal panning requires the
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* plane stride to be a multiple of 4. We'll just
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* require the entire fb to accommodate that to avoid
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* potential runtime errors at plane configuration time.
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*/
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if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
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color_plane == 0 && fb->width > 3840)
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tile_width *= 4;
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/*
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* The main surface pitch must be padded to a multiple of four
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* tile widths.
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*/
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else if (DISPLAY_VER(dev_priv) >= 12)
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tile_width *= 4;
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}
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return tile_width;
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}
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static struct i915_vma *
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initial_plane_vma(struct drm_i915_private *i915,
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struct intel_initial_plane_config *plane_config)
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@ -6182,28 +6092,6 @@ static const struct drm_display_mode load_detect_mode = {
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704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
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};
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struct drm_framebuffer *
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intel_framebuffer_create(struct drm_i915_gem_object *obj,
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struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct intel_framebuffer *intel_fb;
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int ret;
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intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
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if (!intel_fb)
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return ERR_PTR(-ENOMEM);
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ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
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if (ret)
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goto err;
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return &intel_fb->base;
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err:
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kfree(intel_fb);
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return ERR_PTR(ret);
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}
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static int intel_modeset_disable_planes(struct drm_atomic_state *state,
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struct drm_crtc *crtc)
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{
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@ -11356,249 +11244,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
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drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
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}
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static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
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{
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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drm_framebuffer_cleanup(fb);
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if (intel_fb_uses_dpt(fb))
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intel_dpt_destroy(intel_fb->dpt_vm);
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intel_frontbuffer_put(intel_fb->frontbuffer);
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kfree(intel_fb);
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}
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static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
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struct drm_file *file,
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unsigned int *handle)
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{
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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if (i915_gem_object_is_userptr(obj)) {
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drm_dbg(&i915->drm,
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"attempting to use a userptr for a framebuffer, denied\n");
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return -EINVAL;
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}
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return drm_gem_handle_create(file, &obj->base, handle);
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}
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static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
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struct drm_file *file,
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unsigned flags, unsigned color,
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struct drm_clip_rect *clips,
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unsigned num_clips)
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{
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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i915_gem_object_flush_if_display(obj);
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intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
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return 0;
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}
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static const struct drm_framebuffer_funcs intel_fb_funcs = {
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.destroy = intel_user_framebuffer_destroy,
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.create_handle = intel_user_framebuffer_create_handle,
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.dirty = intel_user_framebuffer_dirty,
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};
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static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
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struct drm_i915_gem_object *obj,
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struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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struct drm_framebuffer *fb = &intel_fb->base;
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u32 max_stride;
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unsigned int tiling, stride;
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int ret = -EINVAL;
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int i;
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intel_fb->frontbuffer = intel_frontbuffer_get(obj);
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if (!intel_fb->frontbuffer)
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return -ENOMEM;
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i915_gem_object_lock(obj, NULL);
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tiling = i915_gem_object_get_tiling(obj);
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stride = i915_gem_object_get_stride(obj);
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i915_gem_object_unlock(obj);
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if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
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/*
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* If there's a fence, enforce that
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* the fb modifier and tiling mode match.
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*/
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if (tiling != I915_TILING_NONE &&
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tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
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drm_dbg_kms(&dev_priv->drm,
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"tiling_mode doesn't match fb modifier\n");
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goto err;
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}
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} else {
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if (tiling == I915_TILING_X) {
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mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
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} else if (tiling == I915_TILING_Y) {
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drm_dbg_kms(&dev_priv->drm,
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"No Y tiling for legacy addfb\n");
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goto err;
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}
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}
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if (!drm_any_plane_has_format(&dev_priv->drm,
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mode_cmd->pixel_format,
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mode_cmd->modifier[0])) {
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drm_dbg_kms(&dev_priv->drm,
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"unsupported pixel format %p4cc / modifier 0x%llx\n",
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&mode_cmd->pixel_format, mode_cmd->modifier[0]);
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goto err;
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}
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/*
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* gen2/3 display engine uses the fence if present,
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* so the tiling mode must match the fb modifier exactly.
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*/
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if (DISPLAY_VER(dev_priv) < 4 &&
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tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
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drm_dbg_kms(&dev_priv->drm,
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"tiling_mode must match fb modifier exactly on gen2/3\n");
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goto err;
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}
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max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
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mode_cmd->modifier[0]);
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if (mode_cmd->pitches[0] > max_stride) {
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drm_dbg_kms(&dev_priv->drm,
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"%s pitch (%u) must be at most %d\n",
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mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
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"tiled" : "linear",
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mode_cmd->pitches[0], max_stride);
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goto err;
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}
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/*
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* If there's a fence, enforce that
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* the fb pitch and fence stride match.
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*/
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if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
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drm_dbg_kms(&dev_priv->drm,
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"pitch (%d) must match tiling stride (%d)\n",
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mode_cmd->pitches[0], stride);
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goto err;
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}
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/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
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if (mode_cmd->offsets[0] != 0) {
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drm_dbg_kms(&dev_priv->drm,
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"plane 0 offset (0x%08x) must be 0\n",
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mode_cmd->offsets[0]);
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goto err;
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}
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drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
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for (i = 0; i < fb->format->num_planes; i++) {
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u32 stride_alignment;
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if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
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drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
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i);
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goto err;
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}
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stride_alignment = intel_fb_stride_alignment(fb, i);
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if (fb->pitches[i] & (stride_alignment - 1)) {
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drm_dbg_kms(&dev_priv->drm,
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"plane %d pitch (%d) must be at least %u byte aligned\n",
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i, fb->pitches[i], stride_alignment);
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goto err;
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}
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if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
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int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
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if (fb->pitches[i] != ccs_aux_stride) {
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drm_dbg_kms(&dev_priv->drm,
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"ccs aux plane %d pitch (%d) must be %d\n",
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i,
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fb->pitches[i], ccs_aux_stride);
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goto err;
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}
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}
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/* TODO: Add POT stride remapping support for CCS formats as well. */
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if (IS_ALDERLAKE_P(dev_priv) &&
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mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
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!intel_fb_needs_pot_stride_remap(intel_fb) &&
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!is_power_of_2(mode_cmd->pitches[i])) {
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drm_dbg_kms(&dev_priv->drm,
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"plane %d pitch (%d) must be power of two for tiled buffers\n",
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i, mode_cmd->pitches[i]);
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goto err;
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}
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fb->obj[i] = &obj->base;
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}
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ret = intel_fill_fb_info(dev_priv, intel_fb);
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if (ret)
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goto err;
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if (intel_fb_uses_dpt(fb)) {
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struct i915_address_space *vm;
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vm = intel_dpt_create(intel_fb);
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if (IS_ERR(vm)) {
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ret = PTR_ERR(vm);
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goto err;
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}
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intel_fb->dpt_vm = vm;
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}
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ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
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if (ret) {
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drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
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goto err;
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}
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return 0;
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err:
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intel_frontbuffer_put(intel_fb->frontbuffer);
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return ret;
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}
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static struct drm_framebuffer *
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intel_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *filp,
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const struct drm_mode_fb_cmd2 *user_mode_cmd)
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{
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struct drm_framebuffer *fb;
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struct drm_i915_gem_object *obj;
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struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
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struct drm_i915_private *i915;
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obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
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if (!obj)
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return ERR_PTR(-ENOENT);
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/* object is backed with LMEM for discrete */
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i915 = to_i915(obj->base.dev);
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if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM)) {
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/* object is "remote", not in local memory */
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i915_gem_object_put(obj);
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return ERR_PTR(-EREMOTE);
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}
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fb = intel_framebuffer_create(obj, &mode_cmd);
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i915_gem_object_put(obj);
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return fb;
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}
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static enum drm_mode_status
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intel_mode_valid(struct drm_device *dev,
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const struct drm_display_mode *mode)
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|
|
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@ -4,9 +4,11 @@
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*/
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_modeset_helper.h>
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|
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#include "intel_display.h"
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#include "intel_display_types.h"
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#include "intel_dpt.h"
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#include "intel_fb.h"
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|
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#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
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|
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@ -61,6 +63,12 @@ int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
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return ccs_plane - fb->format->num_planes / 2;
|
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}
|
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|
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static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
|
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{
|
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return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
|
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512) * 64;
|
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}
|
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|
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int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
|
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{
|
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struct drm_i915_private *i915 = to_i915(fb->dev);
|
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|
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@ -172,6 +180,22 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
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return ALIGN(height, tile_height);
|
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}
|
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|
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static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
|
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{
|
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switch (fb_modifier) {
|
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case I915_FORMAT_MOD_X_TILED:
|
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return I915_TILING_X;
|
||||
case I915_FORMAT_MOD_Y_TILED:
|
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case I915_FORMAT_MOD_Y_TILED_CCS:
|
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case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
|
||||
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
|
||||
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
|
||||
return I915_TILING_Y;
|
||||
default:
|
||||
return I915_TILING_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
|
||||
{
|
||||
if (IS_I830(i915))
|
||||
|
|
@ -1045,6 +1069,71 @@ void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotatio
|
|||
*view = fb->normal_view;
|
||||
}
|
||||
|
||||
static
|
||||
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
|
||||
u32 pixel_format, u64 modifier)
|
||||
{
|
||||
/*
|
||||
* Arbitrary limit for gen4+ chosen to match the
|
||||
* render engine max stride.
|
||||
*
|
||||
* The new CCS hash mode makes remapping impossible
|
||||
*/
|
||||
if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
|
||||
intel_modifier_uses_dpt(dev_priv, modifier))
|
||||
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
|
||||
else if (DISPLAY_VER(dev_priv) >= 7)
|
||||
return 256 * 1024;
|
||||
else
|
||||
return 128 * 1024;
|
||||
}
|
||||
|
||||
static u32
|
||||
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(fb->dev);
|
||||
u32 tile_width;
|
||||
|
||||
if (is_surface_linear(fb, color_plane)) {
|
||||
u32 max_stride = intel_plane_fb_max_stride(dev_priv,
|
||||
fb->format->format,
|
||||
fb->modifier);
|
||||
|
||||
/*
|
||||
* To make remapping with linear generally feasible
|
||||
* we need the stride to be page aligned.
|
||||
*/
|
||||
if (fb->pitches[color_plane] > max_stride &&
|
||||
!is_ccs_modifier(fb->modifier))
|
||||
return intel_tile_size(dev_priv);
|
||||
else
|
||||
return 64;
|
||||
}
|
||||
|
||||
tile_width = intel_tile_width_bytes(fb, color_plane);
|
||||
if (is_ccs_modifier(fb->modifier)) {
|
||||
/*
|
||||
* Display WA #0531: skl,bxt,kbl,glk
|
||||
*
|
||||
* Render decompression and plane width > 3840
|
||||
* combined with horizontal panning requires the
|
||||
* plane stride to be a multiple of 4. We'll just
|
||||
* require the entire fb to accommodate that to avoid
|
||||
* potential runtime errors at plane configuration time.
|
||||
*/
|
||||
if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
|
||||
color_plane == 0 && fb->width > 3840)
|
||||
tile_width *= 4;
|
||||
/*
|
||||
* The main surface pitch must be padded to a multiple of four
|
||||
* tile widths.
|
||||
*/
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
tile_width *= 4;
|
||||
}
|
||||
return tile_width;
|
||||
}
|
||||
|
||||
static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
|
||||
|
|
@ -1108,3 +1197,268 @@ int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
|
|||
|
||||
return intel_plane_check_stride(plane_state);
|
||||
}
|
||||
|
||||
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
||||
{
|
||||
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
|
||||
|
||||
drm_framebuffer_cleanup(fb);
|
||||
|
||||
if (intel_fb_uses_dpt(fb))
|
||||
intel_dpt_destroy(intel_fb->dpt_vm);
|
||||
|
||||
intel_frontbuffer_put(intel_fb->frontbuffer);
|
||||
|
||||
kfree(intel_fb);
|
||||
}
|
||||
|
||||
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
||||
struct drm_file *file,
|
||||
unsigned int *handle)
|
||||
{
|
||||
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
|
||||
struct drm_i915_private *i915 = to_i915(obj->base.dev);
|
||||
|
||||
if (i915_gem_object_is_userptr(obj)) {
|
||||
drm_dbg(&i915->drm,
|
||||
"attempting to use a userptr for a framebuffer, denied\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return drm_gem_handle_create(file, &obj->base, handle);
|
||||
}
|
||||
|
||||
static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
|
||||
struct drm_file *file,
|
||||
unsigned int flags, unsigned int color,
|
||||
struct drm_clip_rect *clips,
|
||||
unsigned int num_clips)
|
||||
{
|
||||
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
|
||||
|
||||
i915_gem_object_flush_if_display(obj);
|
||||
intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_framebuffer_funcs intel_fb_funcs = {
|
||||
.destroy = intel_user_framebuffer_destroy,
|
||||
.create_handle = intel_user_framebuffer_create_handle,
|
||||
.dirty = intel_user_framebuffer_dirty,
|
||||
};
|
||||
|
||||
int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
|
||||
struct drm_i915_gem_object *obj,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
|
||||
struct drm_framebuffer *fb = &intel_fb->base;
|
||||
u32 max_stride;
|
||||
unsigned int tiling, stride;
|
||||
int ret = -EINVAL;
|
||||
int i;
|
||||
|
||||
intel_fb->frontbuffer = intel_frontbuffer_get(obj);
|
||||
if (!intel_fb->frontbuffer)
|
||||
return -ENOMEM;
|
||||
|
||||
i915_gem_object_lock(obj, NULL);
|
||||
tiling = i915_gem_object_get_tiling(obj);
|
||||
stride = i915_gem_object_get_stride(obj);
|
||||
i915_gem_object_unlock(obj);
|
||||
|
||||
if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
|
||||
/*
|
||||
* If there's a fence, enforce that
|
||||
* the fb modifier and tiling mode match.
|
||||
*/
|
||||
if (tiling != I915_TILING_NONE &&
|
||||
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"tiling_mode doesn't match fb modifier\n");
|
||||
goto err;
|
||||
}
|
||||
} else {
|
||||
if (tiling == I915_TILING_X) {
|
||||
mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
|
||||
} else if (tiling == I915_TILING_Y) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"No Y tiling for legacy addfb\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
if (!drm_any_plane_has_format(&dev_priv->drm,
|
||||
mode_cmd->pixel_format,
|
||||
mode_cmd->modifier[0])) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"unsupported pixel format %p4cc / modifier 0x%llx\n",
|
||||
&mode_cmd->pixel_format, mode_cmd->modifier[0]);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* gen2/3 display engine uses the fence if present,
|
||||
* so the tiling mode must match the fb modifier exactly.
|
||||
*/
|
||||
if (DISPLAY_VER(dev_priv) < 4 &&
|
||||
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"tiling_mode must match fb modifier exactly on gen2/3\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
|
||||
mode_cmd->modifier[0]);
|
||||
if (mode_cmd->pitches[0] > max_stride) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"%s pitch (%u) must be at most %d\n",
|
||||
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
|
||||
"tiled" : "linear",
|
||||
mode_cmd->pitches[0], max_stride);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* If there's a fence, enforce that
|
||||
* the fb pitch and fence stride match.
|
||||
*/
|
||||
if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"pitch (%d) must match tiling stride (%d)\n",
|
||||
mode_cmd->pitches[0], stride);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
|
||||
if (mode_cmd->offsets[0] != 0) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"plane 0 offset (0x%08x) must be 0\n",
|
||||
mode_cmd->offsets[0]);
|
||||
goto err;
|
||||
}
|
||||
|
||||
drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
|
||||
|
||||
for (i = 0; i < fb->format->num_planes; i++) {
|
||||
u32 stride_alignment;
|
||||
|
||||
if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
|
||||
drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
|
||||
i);
|
||||
goto err;
|
||||
}
|
||||
|
||||
stride_alignment = intel_fb_stride_alignment(fb, i);
|
||||
if (fb->pitches[i] & (stride_alignment - 1)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"plane %d pitch (%d) must be at least %u byte aligned\n",
|
||||
i, fb->pitches[i], stride_alignment);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
|
||||
int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
|
||||
|
||||
if (fb->pitches[i] != ccs_aux_stride) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"ccs aux plane %d pitch (%d) must be %d\n",
|
||||
i,
|
||||
fb->pitches[i], ccs_aux_stride);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
/* TODO: Add POT stride remapping support for CCS formats as well. */
|
||||
if (IS_ALDERLAKE_P(dev_priv) &&
|
||||
mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
|
||||
!intel_fb_needs_pot_stride_remap(intel_fb) &&
|
||||
!is_power_of_2(mode_cmd->pitches[i])) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"plane %d pitch (%d) must be power of two for tiled buffers\n",
|
||||
i, mode_cmd->pitches[i]);
|
||||
goto err;
|
||||
}
|
||||
|
||||
fb->obj[i] = &obj->base;
|
||||
}
|
||||
|
||||
ret = intel_fill_fb_info(dev_priv, intel_fb);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
if (intel_fb_uses_dpt(fb)) {
|
||||
struct i915_address_space *vm;
|
||||
|
||||
vm = intel_dpt_create(intel_fb);
|
||||
if (IS_ERR(vm)) {
|
||||
ret = PTR_ERR(vm);
|
||||
goto err;
|
||||
}
|
||||
|
||||
intel_fb->dpt_vm = vm;
|
||||
}
|
||||
|
||||
ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
|
||||
if (ret) {
|
||||
drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
intel_frontbuffer_put(intel_fb->frontbuffer);
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct drm_framebuffer *
|
||||
intel_user_framebuffer_create(struct drm_device *dev,
|
||||
struct drm_file *filp,
|
||||
const struct drm_mode_fb_cmd2 *user_mode_cmd)
|
||||
{
|
||||
struct drm_framebuffer *fb;
|
||||
struct drm_i915_gem_object *obj;
|
||||
struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
|
||||
struct drm_i915_private *i915;
|
||||
|
||||
obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
|
||||
if (!obj)
|
||||
return ERR_PTR(-ENOENT);
|
||||
|
||||
/* object is backed with LMEM for discrete */
|
||||
i915 = to_i915(obj->base.dev);
|
||||
if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM)) {
|
||||
/* object is "remote", not in local memory */
|
||||
i915_gem_object_put(obj);
|
||||
return ERR_PTR(-EREMOTE);
|
||||
}
|
||||
|
||||
fb = intel_framebuffer_create(obj, &mode_cmd);
|
||||
i915_gem_object_put(obj);
|
||||
|
||||
return fb;
|
||||
}
|
||||
|
||||
struct drm_framebuffer *
|
||||
intel_framebuffer_create(struct drm_i915_gem_object *obj,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd)
|
||||
{
|
||||
struct intel_framebuffer *intel_fb;
|
||||
int ret;
|
||||
|
||||
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
|
||||
if (!intel_fb)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
return &intel_fb->base;
|
||||
|
||||
err:
|
||||
kfree(intel_fb);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,10 +8,12 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct drm_device;
|
||||
struct drm_file;
|
||||
struct drm_framebuffer;
|
||||
|
||||
struct drm_i915_gem_object;
|
||||
struct drm_i915_private;
|
||||
|
||||
struct drm_mode_fb_cmd2;
|
||||
struct intel_fb_view;
|
||||
struct intel_framebuffer;
|
||||
struct intel_plane_state;
|
||||
|
|
@ -57,4 +59,12 @@ void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotatio
|
|||
struct intel_fb_view *view);
|
||||
int intel_plane_compute_gtt(struct intel_plane_state *plane_state);
|
||||
|
||||
int intel_framebuffer_init(struct intel_framebuffer *ifb,
|
||||
struct drm_i915_gem_object *obj,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd);
|
||||
struct drm_framebuffer *
|
||||
intel_user_framebuffer_create(struct drm_device *dev,
|
||||
struct drm_file *filp,
|
||||
const struct drm_mode_fb_cmd2 *user_mode_cmd);
|
||||
|
||||
#endif /* __INTEL_FB_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user