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media: ipu6: Add IPU8 psys MMU table and PLL power sequencing
Port the remaining IPU8 psys platform enablement that already exists upstream in staging ipu7: the psys MMU hardware table and PLL request/release in the shared power-on/off path. This driver has no psys pipeline consumer, so it only affects the psys bus device's power sequencing and MMU setup. Signed-off-by: Divyamani Tripathi <divyamani.tripathi@intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
This commit is contained in:
Divyamani Tripathi
Sakari Ailus
parent
9b7938dbd7
commit
7016542588
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@ -512,6 +512,17 @@ static int __ipu7_power_on(struct device *dev,
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ipu7_nde_control(isp, true);
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}
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/* IPU8 psys needs its PLL running above 400MHz. */
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if (!is_isys && IS_IPU8(isp) && ctrl->ratio > IPU8_PS_FREQ_CTL_DEFAULT_RATIO) {
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writel(1, isp->base + IPU7_BUTTRESS_REG_PS_PLL_ENABLE);
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ret = readl_poll_timeout(isp->base + IPU7_BUTTRESS_REG_SLEEP_LEVEL_STS,
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val, (val & IPU7_BUTTRESS_OWN_ACK_PS_CLK),
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100, BUTTRESS_POWER_TIMEOUT_US);
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if (ret)
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dev_warn(&isp->pdev->dev,
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"ps_pll req ack timeout: 0x%x\n", val);
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}
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/* Request clock ownership. */
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ovrd_clk = is_isys ? IPU7_BUTTRESS_OVERRIDE_IS_CLK :
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IPU7_BUTTRESS_OVERRIDE_PS_CLK;
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@ -569,6 +580,12 @@ static int __ipu7_power_off(struct device *dev,
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ipu7_nde_control(isp, false);
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}
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if (ctrl->subsys_id == IPU_PSYS && IS_IPU8(isp)) {
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val = readl(isp->base + IPU7_BUTTRESS_REG_SLEEP_LEVEL_STS);
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if (val & IPU7_BUTTRESS_OWN_ACK_PS_CLK)
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writel(0, isp->base + IPU7_BUTTRESS_REG_PS_PLL_ENABLE);
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}
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return 0;
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}
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@ -282,6 +282,9 @@ enum {
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#define IPU7_BUTTRESS_IS_FREQ_CTL_RATIO_MASK GENMASK(7, 0)
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#define IPU7_IS_FREQ_CTL_DEFAULT_RATIO 0x1b
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#define IPU7_PS_FREQ_CTL_DEFAULT_RATIO 0x14
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/* IS: 400MHz, PS: 400MHz */
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#define IPU8_IS_FREQ_CTL_DEFAULT_RATIO 0x10
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#define IPU8_PS_FREQ_CTL_DEFAULT_RATIO 0x10
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/* D2D power control */
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#define IPU7_BUTTRESS_REG_D2D_CTL 0x21d4
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@ -320,6 +323,7 @@ enum {
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#define IPU7_BUTTRESS_OWN_ACK_IS_CLK BIT(9)
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#define IPU7_BUTTRESS_OVERRIDE_PS_CLK BIT(2)
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#define IPU7_BUTTRESS_OWN_ACK_PS_CLK BIT(10)
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#define IPU7_BUTTRESS_REG_PS_PLL_ENABLE 0x21bc
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/* PB registers */
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#define IPU7_GLOBAL_INTERRUPT_MASK 0x8
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@ -538,6 +538,128 @@ static struct ipu7_mmu_hw ipu7p5_isys_mmu_hwdata[] = {
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},
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};
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static struct ipu7_mmu_hw ipu8_psys_mmu_hwdata[] = {
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{
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.name = "PS_FW_RD",
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.offset = IPU8_PS_MMU_FW_RD_OFFSET,
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.zlx_offset = IPU8_PS_ZLX_FW_RD_OFFSET,
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.uao_offset = IPU8_PS_UAO_FW_RD_OFFSET,
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.info_bits = 0x20003a01,
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.refill = 0x00002726,
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.collapse_en_bitmap = 0x1,
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.at_sp_arb_cfg = 0x1,
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.l1_block = IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG,
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.l2_block = IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG,
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.nr_l1streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
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.nr_l2streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
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.l1_block_sz = { 0x00, 0x08, 0x0a, 0x0e, 0x10, 0x12, 0x14, 0x16,
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0x18, 0x18, 0x18, 0x18 },
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.l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
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0x10, 0x12, 0x14, 0x16 },
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.zlx_nr = IPU8_PS_ZLX_FW_RD_NUM,
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.zlx_axi_pool = { 0x00000f30 },
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.zlx_en = { 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 },
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.zlx_conf = { 0x0, 0x2, 0x0, 0x0, 0x2, 0x2, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0 },
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.uao_p_num = IPU8_PS_UAO_FW_RD_PLANENUM,
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.uao_p2tlb = { 0x2d, 0x32, 0x33, 0x30, 0x34, 0x35, 0x36, 0x31,
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0x0, 0x0, 0x0, 0x0 },
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},
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{
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.name = "PS_FW_WR",
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.offset = IPU8_PS_MMU_FW_WR_OFFSET,
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.zlx_offset = IPU8_PS_ZLX_FW_WR_OFFSET,
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.uao_offset = IPU8_PS_UAO_FW_WR_OFFSET,
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.info_bits = 0x20003901,
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.refill = 0x00002524,
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.collapse_en_bitmap = 0x1,
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.at_sp_arb_cfg = 0x1,
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.l1_block = IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG,
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.l2_block = IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG,
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.nr_l1streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
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.nr_l2streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
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.l1_block_sz = { 0x00, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x10, 0x10 },
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.l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e },
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.zlx_nr = IPU8_PS_ZLX_FW_WR_NUM,
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.zlx_axi_pool = { 0x00000f20 },
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.zlx_en = { 0, 1, 1, 0, 0, 0, 0, 0 },
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.zlx_conf = { 0x0, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0 },
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.uao_p_num = IPU8_PS_UAO_FW_WR_PLANENUM,
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.uao_p2tlb = { 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x0, 0x0, 0x0 },
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},
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{
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.name = "PS_DATA_RD",
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.offset = IPU8_PS_MMU_SRT_RD_OFFSET,
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.zlx_offset = IPU8_PS_ZLX_DATA_RD_OFFSET,
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.uao_offset = IPU8_PS_UAO_SRT_RD_OFFSET,
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.info_bits = 0x20003801,
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.refill = 0x00002322,
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.collapse_en_bitmap = 0x1,
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.at_sp_arb_cfg = 0x1,
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.l1_block = IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
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.l2_block = IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
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.nr_l1streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
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.nr_l2streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
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.l1_block_sz = { 0x00, 0x04, 0x06, 0x08, 0x0c, 0x0e, 0x10, 0x14,
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0x18, 0x1c, 0x1e, 0x22, 0x24, 0x26, 0x28, 0x2a,
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0x2c, 0x2e, 0x30, 0x32, 0x36, 0x3a, 0x3c, 0x3c,
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0x3c, 0x3c },
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.l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
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0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
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0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
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0x30, 0x32 },
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.zlx_nr = IPU8_PS_ZLX_DATA_RD_NUM,
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.zlx_axi_pool = { 0x00000f30 },
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.zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
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.zlx_conf = { 0x6, 0x3, 0x3, 0x6, 0x2, 0x2, 0x6, 0x6,
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0x6, 0x3, 0x6, 0x3, 0x3, 0x2, 0x2, 0x2,
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0x2, 0x2, 0x2, 0x6, 0x6, 0x3, 0x0, 0x0,
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0x0, 0x0 },
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.uao_p_num = IPU8_PS_UAO_SRT_RD_PLANENUM,
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.uao_p2tlb = { 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e,
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0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
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0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x0, 0x0,
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0x0, 0x0 },
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},
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{
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.name = "PS_DATA_WR",
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.offset = IPU8_PS_MMU_SRT_WR_OFFSET,
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.zlx_offset = IPU8_PS_ZLX_DATA_WR_OFFSET,
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.uao_offset = IPU8_PS_UAO_SRT_WR_OFFSET,
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.info_bits = 0x20003701,
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.refill = 0x00002120,
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.collapse_en_bitmap = 0x1,
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.at_sp_arb_cfg = 0x1,
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.l1_block = IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
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.l2_block = IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
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.nr_l1streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
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.nr_l2streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
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.l1_block_sz = { 0x00, 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
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0x12, 0x14, 0x16, 0x18, 0x1c, 0x1e, 0x22, 0x24,
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0x28, 0x2a, 0x2e, 0x30, 0x32, 0x36, 0x38, 0x3a,
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0x3a, 0x3a },
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.l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
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0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
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0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
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0x30, 0x32 },
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.zlx_nr = IPU8_PS_ZLX_DATA_WR_NUM,
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.zlx_axi_pool = { 0x00000f50 },
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.zlx_en = { 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
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.zlx_conf = { 0x3, 0x6, 0x38000002, 0x38000000, 0x3, 0x38000002,
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0x38000002, 0x38000002, 0x38000002, 0x38000002,
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0x38000002, 0x6, 0x3, 0x6, 0x3, 0x6,
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0x3, 0x6, 0x3, 0x3, 0x6, 0x3, 0x3, 0x0,
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0x0, 0x0 },
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.uao_p_num = IPU8_PS_UAO_SRT_WR_PLANENUM,
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.uao_p2tlb = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x00,
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0x00, 0x00 },
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},
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};
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static struct ipu7_mmu_hw ipu8_isys_mmu_hwdata[] = {
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{
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.name = "IS_FW_RD",
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@ -818,15 +940,10 @@ static const struct ipu7_mmu_hwdata ipu7p5_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
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},
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};
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/*
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* IPU8 has no dedicated psys MMU table upstream (psys pipeline
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* support is not targeted for this driver); reuse the IPU7P5 psys
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* table as a placeholder so the psys bus device still initialises.
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*/
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static const struct ipu7_mmu_hwdata ipu8_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
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[IPU_PSYS] = {
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.hwdata = ipu7p5_psys_mmu_hwdata,
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.nr_mmus = ARRAY_SIZE(ipu7p5_psys_mmu_hwdata),
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.hwdata = ipu8_psys_mmu_hwdata,
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.nr_mmus = ARRAY_SIZE(ipu8_psys_mmu_hwdata),
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},
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[IPU_ISYS] = {
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.hwdata = ipu8_isys_mmu_hwdata,
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@ -277,6 +277,57 @@
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#define IPU8_IS_MMU_NUM 5U
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/* PS MMU FW RD */
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#define IPU8_PS_MMU_FW_RD_OFFSET 0x148000
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#define IPU8_PS_MMU_FW_RD_STREAM_NUM 12
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#define IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG 0x54
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#define IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG 0x84
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/* PS MMU FW WR */
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#define IPU8_PS_MMU_FW_WR_OFFSET 0x149000
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#define IPU8_PS_MMU_FW_WR_STREAM_NUM 8
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#define IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG 0x54
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#define IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG 0x74
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/* PS MMU FW Data RD VC0 */
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#define IPU8_PS_MMU_SRT_RD_OFFSET 0x14a000
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#define IPU8_PS_MMU_SRT_RD_STREAM_NUM 26
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#define IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG 0x54
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#define IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG 0xbc
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/* PS MMU FW Data WR VC0 */
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#define IPU8_PS_MMU_SRT_WR_OFFSET 0x14b000
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#define IPU8_PS_MMU_SRT_WR_STREAM_NUM 26
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#define IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG 0x54
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#define IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG 0xbc
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/* PS UAO FW RD */
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#define IPU8_PS_UAO_FW_RD_OFFSET 0x156000
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#define IPU8_PS_UAO_FW_RD_PLANENUM 12
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/* PS UAO FW WR */
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#define IPU8_PS_UAO_FW_WR_OFFSET 0x157000
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#define IPU8_PS_UAO_FW_WR_PLANENUM 8
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/* PS UAO SRT RD */
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#define IPU8_PS_UAO_SRT_RD_OFFSET 0x154000
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#define IPU8_PS_UAO_SRT_RD_PLANENUM 26
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/* PS UAO SRT WR */
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#define IPU8_PS_UAO_SRT_WR_OFFSET 0x155000
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#define IPU8_PS_UAO_SRT_WR_PLANENUM 26
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#define IPU8_PS_ZLX_DATA_RD_OFFSET 0x14e000
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#define IPU8_PS_ZLX_DATA_WR_OFFSET 0x14f000
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#define IPU8_PS_ZLX_FW_RD_OFFSET 0x150000
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#define IPU8_PS_ZLX_FW_WR_OFFSET 0x151000
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#define IPU8_PS_ZLX_DATA_RD_NUM 26
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#define IPU8_PS_ZLX_DATA_WR_NUM 26
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#define IPU8_PS_ZLX_FW_RD_NUM 12
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#define IPU8_PS_ZLX_FW_WR_NUM 8
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#define IPU8_PS_MMU_NUM 4U
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struct ipu7_mmu_hw {
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char name[32];
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