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net: stmmac: eswin: correct RGMII delay granularity to 20 ps

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The EIC7700 MAC implements programmable RGMII delay adjustment with a
granularity of 20 ps per hardware step.

The driver previously converted rx-internal-delay-ps and
tx-internal-delay-ps values using a 100 ps step size, resulting in
incorrect delay programming.

Update the conversion to use the correct 20 ps granularity so the
programmed delay matches the values described in the device tree.

Fixes: ea77dbbdbc ("net: stmmac: add Eswin EIC7700 glue driver")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Link: https://patch.msgid.link/20260518022156.484-1-lizhi2@eswincomputing.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Zhi Li 2026-05-18 10:21:52 +08:00 committed by Paolo Abeni
parent 6872fb088e
commit 6ffcef9bc1
1 changed files with 4 additions and 4 deletions
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8
drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
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@ -28,8 +28,8 @@
/*
* TX/RX Clock Delay Bit Masks:
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
*/
#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
@ -148,7 +148,7 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
/* Read rx-internal-delay-ps and update rx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"rx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
u32 val = min(delay_ps / 20, EIC7700_MAX_DELAY_UNIT);
dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
dwc_priv->eth_clk_dly_param |=
@ -161,7 +161,7 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
/* Read tx-internal-delay-ps and update tx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"tx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
u32 val = min(delay_ps / 20, EIC7700_MAX_DELAY_UNIT);
dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
dwc_priv->eth_clk_dly_param |=