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Microchip ARM64 device tree updates for v7.3
This update includes: - the device tree nodes for the QSPI controllers on LAN9691 SoC -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCantS2wAKCRCejrg/N2X7 /fM7AQDb2r71r9KkeT24k8OUNBqsEXt9orXESYoDts/2fmN6KgEAwxBMCm+3jQpZ uUy3uqrz+seNjlESHu9XOkklar+6Hww= =ypm1 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp84iwACgkQmmx57+YA GNnHSRAAg+ljdVQUL2ktpSfzom3vgu/wA5NsahS0qLmktOluznSF0TI3RVYN1tP3 2ZgvxgH9kiVUp3c9NfItFvGcxf4zKlB6pnySqolSoFLP2a85hEgA7o42JQontxm1 A5irV7rBXzNmaVD25FnaCNWTJFXVGg7u4ytlMZXqk0cxEDPDXSBdTiQT79VpRTbG K1AaVYfHPkUx5bUNLDVvOJaph0RwMMwTjDqMg40f/D9FSfasayPAWSUKtQns0j70 5nQBqiUJHkjhY7LICqHuhVTGt20NSX0neDNQmKmfX0RXuE6fH1Gtc9aFH1iVz06F /iCW99dr/4b6LtniE10nNAZmOQ7A3nuJnIg28LBadB6HUiuoZML8cHI0zCxVqRv0 b8MSSZ3pbxn41xS1E/ZPahFbwybJ0W7R6Qre3e9aBxY+COY/6n8srvx7+pehkX9G od2soA4U1g5DITFIryoOFEMlEcZ7XYaS8D/M0qPkpcplwTNTbdVQR9km4mkE+XNr xv3NXl1oDx6vTcOcB+gdNqB8koA1C5PpswWAdSIJXwgopKpbvE8iT2P+oh2ijB6y h3xfNhPbKn1ORyZQgfz6TEXt2Duk7GEgNzeAlkN+7+SHrmy2m4QdJfOsAjv2eTsu DsZoF/oiCXsUorD17IWbb6fy9/y8HiBQ9juqUqC/uoZ03Cr6iWI= =2KDk -----END PGP SIGNATURE----- Merge tag 'microchip-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt Microchip ARM64 device tree updates for v7.3 This update includes: - the device tree nodes for the QSPI controllers on LAN9691 SoC * tag 'microchip-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: arm64: dts: microchip: lan969x: add QSPI nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
6fdec78001
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@ -396,6 +396,39 @@ clks: clock-controller@e00c00b4 {
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clock-names = "cpu", "ddr", "sys";
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};
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qspi0: spi@e0804000 {
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compatible = "microchip,lan9691-qspi";
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reg = <0xe0804000 0x00000100>,
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<0x20000000 0x08000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&clks GCK_ID_QSPI0>;
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assigned-clock-rates = <100000000>;
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dmas = <&dma AT91_XDMAC_DT_PERID(1)>,
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<&dma AT91_XDMAC_DT_PERID(0)>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi2: spi@e0834000 {
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compatible = "microchip,lan9691-qspi";
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reg = <0xe0834000 0x00000100>,
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<0x30000000 0x04000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&clks GCK_ID_QSPI2>;
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assigned-clock-rates = <100000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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reset: reset-controller@e201000c {
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compatible = "microchip,lan9691-switch-reset",
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"microchip,lan966x-switch-reset";
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