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drm/i915/display: Move CMRR crtc_state members under VRR

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Move CMRR crtc state members under VRR infrastructure as
it is enabled during fixed-refresh-rate VRR timing generator
is enabled.

--v2:
- Move cmrr structure under vrr umbrella.
- Remove dups. (Jani)

--v3:
- Update commit message

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260730105919.3913412-6-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani 2026-07-30 16:29:12 +05:30 committed by Suraj Kandpal
parent 77ce0fb5f7
commit 6f80bda1d0
6 changed files with 29 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/display/intel_cmtg.c
View File

@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
/* TODO: The code below may need to be revisited once CMRR is enabled */
if (crtc_state->cmrr.enable)
if (crtc_state->vrr.cmrr.enable)
vrr_ctl |= VRR_CTL_CMRR_ENABLE;
intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);

10
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
}
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@ -5536,9 +5536,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(cmrr.enable);
PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);

12
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1408,13 +1408,13 @@ struct intel_crtc_state {
u16 max_increase, max_decrease;
u16 vblank_target;
} dc_balance;
} vrr;
/* Content Match Refresh Rate state */
struct {
bool enable;
u64 cmrr_n, cmrr_m;
} cmrr;
/* Content Match Refresh Rate state */
struct {
bool enable;
u64 cmrr_n, cmrr_m;
} cmrr;
} vrr;
/* Stream Splitter for eDP MSO */
struct {

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -3104,7 +3104,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
as_sdp->revision = 0x2;
as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
if (crtc_state->cmrr.enable) {
if (crtc_state->vrr.cmrr.enable) {
as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);

2
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -1491,7 +1491,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
if (crtc_state->cmrr.enable) {
if (crtc_state->vrr.cmrr.enable) {
drm_dbg_kms(display->drm,
"PSR2 cannot be enabled when CMRR is enabled\n");
return false;

30
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -235,12 +235,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
multiplier_n = 1000;
}
crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
multiplier_n);
crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
multiplier_n);
vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
crtc_state->cmrr.cmrr_n);
crtc_state->vrr.cmrr.cmrr_n);
adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
return vtotal;
}
@ -258,7 +258,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmin = crtc_state->vrr.vmax;
crtc_state->vrr.flipline = crtc_state->vrr.vmin;
crtc_state->cmrr.enable = true;
crtc_state->vrr.cmrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
@ -651,15 +651,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
if (crtc_state->cmrr.enable) {
if (crtc_state->vrr.cmrr.enable) {
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_m));
upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_m));
lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_n));
upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_n));
lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
}
intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
@ -980,7 +980,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@ -1077,12 +1077,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_VRR_CTL(display, cpu_transcoder));
if (intel_vrr_cmrr_possible(crtc_state))
crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
if (crtc_state->vrr.cmrr.enable) {
crtc_state->vrr.cmrr.cmrr_n =
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
crtc_state->cmrr.cmrr_m =
crtc_state->vrr.cmrr.cmrr_m =
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
}