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arm64: dts: imx8mp-evk: add camera ov5640 and related nodes
Add camera ov5640 and related nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -84,6 +84,27 @@ pcie0_refclk: pcie0-refclk {
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clock-frequency = <100000000>;
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};
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reg_1v5: regulator-1v5 {
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compatible = "regulator-fixed";
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regulator-name = "1v5";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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};
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reg_1v8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_2v8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "2v8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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reg_audio_3v3: regulator-audio-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "audio-3v3";
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@ -548,6 +569,30 @@ &i2c2 {
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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camera@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
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clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
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clock-names = "xclk";
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assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
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assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
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assigned-clock-rates = <24000000>;
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powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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AVDD-supply = <®_2v8>;
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DVDD-supply = <®_1v5>;
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DOVDD-supply = <®_1v8>;
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status = "okay";
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port {
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ov5640_mipi_0_ep: endpoint {
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remote-endpoint = <&mipi_csi0_ep>;
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data-lanes = <1 2>;
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};
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};
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};
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hdmi@3d {
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compatible = "adi,adv7535";
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reg = <0x3d>;
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@ -652,6 +697,10 @@ &i2c5 {
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*/
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};
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&isi_0 {
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status = "okay";
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};
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&lcdif1 {
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status = "okay";
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};
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@ -670,6 +719,19 @@ &micfil {
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status = "okay";
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};
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&mipi_csi_0 {
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status = "okay";
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ports {
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port@0 {
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mipi_csi0_ep: endpoint {
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remote-endpoint = <&ov5640_mipi_0_ep>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi_dsi {
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samsung,esc-clock-frequency = <10000000>;
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status = "okay";
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@ -843,6 +905,24 @@ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
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>;
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};
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pinctrl_csi_mclk: csi_mclk_grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50
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>;
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};
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pinctrl_csi0_pwn: csi0_pwn_grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10
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>;
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};
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pinctrl_csi0_rst: csi0_rst_grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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