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wifi: rtw89: 8852ce: set offset K of PCI PHY EQ to manual mode to improve compatibility

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Read calibration value of PCI RX offset, and set to manual mode as the
value at PCI probe to prevent abnormal calibration results at runtime.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20240925013901.9835-5-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2024-09-25 09:39:01 +08:00
parent c76afc421c
commit 6f46547d3d
1 changed files with 24 additions and 0 deletions
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24
drivers/net/wireless/realtek/rtw89/pci.c
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@ -2363,8 +2363,10 @@ static void rtw89_pci_disable_eq_ax(struct rtw89_dev *rtwdev)
u16 g1_oobs, g2_oobs;
u32 backup_aspm;
u32 phy_offset;
u16 offset_cal;
u16 oobs_val;
int ret;
u8 gen;
if (rtwdev->chip->chip_id != RTL8852C)
return;
@ -2400,6 +2402,28 @@ static void rtw89_pci_disable_eq_ax(struct rtw89_dev *rtwdev)
rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA09 * RAC_MULT,
BAC_OOBS_SEL);
/* offset K */
for (gen = 1; gen <= 2; gen++) {
phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 :
R_RAC_DIRECT_OFFSET_G2;
rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
B_PCIE_BIT_RD_SEL);
}
offset_cal = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 +
RAC_ANA1F * RAC_MULT, OFFSET_CAL_MASK);
for (gen = 1; gen <= 2; gen++) {
phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 :
R_RAC_DIRECT_OFFSET_G2;
rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT,
MANUAL_LVL_MASK, offset_cal);
rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
OFFSET_CAL_MODE);
}
out:
rtw89_write32(rtwdev, R_AX_PCIE_MIX_CFG_V1, backup_aspm);
}