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arm64: dts: rockchip: add reset control registers for rk3399 dp driver.

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Change-Id: Ibbad2bd5ab49c71385045ca743740cbba8ed6bf0
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
This commit is contained in:
wenping.zhang 2016-10-17 10:30:13 +08:00 committed by Huang, Tao
parent a860c496e5
commit 6f2a45a957
1 changed files with 5 additions and 4 deletions
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9
arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
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@ -167,14 +167,15 @@ cdn_dp_fb: dp-fb@fec00000 {
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>;
clock-names = "core-clk", "pclk", "spdif";
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>;
reset-names = "spdif";
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
<&cru SRST_P_UPHY0_APB>;
reset-names = "spdif", "dptx", "apb";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;