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soc/tegra: fuse: Update nvmem cell list

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Update tegra_fuse_cells with below entries:

 - gcplex-config-fuse:
     Configuration bits for GPU, used to enable/disable write protected
     region used for storing GPU firmware.
 - pdi0:
     Unique per chip public identifier.
 - pdi1:
     Unique per chip public identifier.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
kartik 2021-12-06 17:22:45 +05:30 committed by Thierry Reding
parent 1e5cf1452e
commit 6f259bf161
1 changed files with 19 additions and 1 deletions
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20
drivers/soc/tegra/fuse/fuse-tegra.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "gcplex-config-fuse",
.offset = 0x1c8,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "tsensor-realignment",
.offset = 0x1fc,
@ -179,6 +185,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "pdi0",
.offset = 0x300,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
}, {
.name = "pdi1",
.offset = 0x304,
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
},
};