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net/mlx5: Add IFC bits and enums for buf_ownership

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Extend structure layouts and defines buf_ownership.
buf_ownership indicates whether the buffer is managed by SW or FW.

Signed-off-by: Oren Sidi <osidi@nvidia.com>
Reviewed-by: Alex Lazar <alazar@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1752734895-257735-3-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Oren Sidi 2025-07-17 09:48:14 +03:00 committed by Leon Romanovsky
parent 438794e93f
commit 6f09ee0b58
1 changed files with 12 additions and 2 deletions
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14
include/linux/mlx5/mlx5_ifc.h
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@ -10474,8 +10474,16 @@ struct mlx5_ifc_pifr_reg_bits {
u8 port_filter_update_en[8][0x20];
};
enum {
MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0,
MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1,
MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2,
};
struct mlx5_ifc_pfcc_reg_bits {
u8 reserved_at_0[0x8];
u8 reserved_at_0[0x4];
u8 buf_ownership[0x2];
u8 reserved_at_6[0x2];
u8 local_port[0x8];
u8 reserved_at_10[0xb];
u8 ppan_mask_n[0x1];
@ -10611,7 +10619,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits {
u8 fec_200G_per_lane_in_pplm[0x1];
u8 reserved_at_1e[0x2a];
u8 fec_100G_per_lane_in_pplm[0x1];
u8 reserved_at_49[0x1f];
u8 reserved_at_49[0xa];
u8 buffer_ownership[0x1];
u8 resereved_at_54[0x14];
u8 fec_50G_per_lane_in_pplm[0x1];
u8 reserved_at_69[0x4];
u8 rx_icrc_encapsulated_counter[0x1];