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clk: renesas: rzg3e: Add support for DSI clocks
RZ/G3E Clock Pulse Generator PLLDSI limits, shared by clock and MIPI DSI driver source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCafiLmgAKCRCKwlD9ZEnx cIWWAQD+e57m9HGyHasn9GsoTyTGQqwnnpBJYluzhWbpQAk4XQD9G1EG968r0KoH EkmFwA2XmllNYXASJB5HKlRLHh8RAQY= =0942 -----END PGP SIGNATURE----- Merge tag 'clk-renesas-rzg3e-plldsi-tag' into renesas-clk-for-v7.2 clk: renesas: rzg3e: Add support for DSI clocks RZ/G3E Clock Pulse Generator PLLDSI limits, shared by clock and MIPI DSI driver source files.
This commit is contained in:
Geert Uytterhoeven
commit
6edb69b808
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@ -6,6 +6,7 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -30,6 +31,8 @@ enum clk_ids {
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CLK_PLLCA55,
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CLK_PLLVDO,
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CLK_PLLETH,
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CLK_PLLDSI0,
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CLK_PLLDSI1,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV3,
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@ -57,6 +60,8 @@ enum clk_ids {
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CLK_PLLETH_DIV_125_FIX,
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CLK_CSDIV_PLLETH_GBE0,
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CLK_CSDIV_PLLETH_GBE1,
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CLK_SMUX2_DSI0_CLK,
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CLK_SMUX2_DSI1_CLK,
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CLK_SMUX2_GBE0_TXCLK,
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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@ -64,6 +69,12 @@ enum clk_ids {
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CLK_PLLDTY_DIV16,
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CLK_PLLVDO_CRU0,
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CLK_PLLVDO_GPU,
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CLK_PLLETH_DIV4_LPCLK,
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CLK_PLLETH_LPCLK,
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CLK_PLLDSI0_DIV7,
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CLK_PLLDSI1_DIV7,
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CLK_PLLDSI0_CSDIV,
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CLK_PLLDSI1_CSDIV,
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/* Module Clocks */
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MOD_CLK_BASE,
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@ -91,6 +102,18 @@ static const struct clk_div_table dtable_2_16[] = {
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{0, 0},
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};
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static const struct clk_div_table dtable_2_16_plldsi[] = {
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{0, 2},
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{1, 4},
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{2, 6},
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{3, 8},
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{4, 10},
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{5, 12},
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{6, 14},
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{7, 16},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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@ -107,7 +130,23 @@ static const struct clk_div_table dtable_2_100[] = {
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{0, 0},
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};
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static const struct clk_div_table dtable_16_128[] = {
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{0, 16},
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{1, 32},
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{2, 64},
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{3, 128},
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{0, 0},
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};
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RZG3E_CPG_PLL_DSI0_LIMITS(rzg3e_cpg_pll_dsi0_limits);
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RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
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#define PLLDSI0 PLL_PACK_LIMITS(0xc0, 1, 0, &rzg3e_cpg_pll_dsi0_limits)
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#define PLLDSI1 PLL_PACK_LIMITS(0x160, 1, 1, &rzg3e_cpg_pll_dsi1_limits)
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/* Mux clock tables */
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static const char * const smux2_dsi0_clk[] = { ".plldsi0_div7", ".plldsi0_csdiv" };
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static const char * const smux2_dsi1_clk[] = { ".plldsi1_div7", ".plldsi1_csdiv" };
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
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static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
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static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
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@ -128,6 +167,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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DEF_PLLDSI(".plldsi0", CLK_PLLDSI0, CLK_QEXTAL, PLLDSI0),
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DEF_PLLDSI(".plldsi1", CLK_PLLDSI1, CLK_QEXTAL, PLLDSI1),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
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@ -171,6 +212,21 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
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DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
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DEF_FIXED(".plleth_div4_lpclk", CLK_PLLETH_DIV4_LPCLK, CLK_PLLETH, 1, 4),
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DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
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CSDIV0_DIVCTL2, dtable_16_128),
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DEF_PLLDSI_DIV(".plldsi0_csdiv", CLK_PLLDSI0_CSDIV, CLK_PLLDSI0,
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CSDIV1_DIVCTL2, dtable_2_16_plldsi),
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DEF_PLLDSI_DIV(".plldsi1_csdiv", CLK_PLLDSI1_CSDIV, CLK_PLLDSI1,
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CSDIV1_DIVCTL3, dtable_2_16_plldsi),
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DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
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DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
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DEF_PLLDSI_SMUX(".smux2_dsi0_clk", CLK_SMUX2_DSI0_CLK,
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SSEL3_SELCTL0, smux2_dsi0_clk),
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DEF_PLLDSI_SMUX(".smux2_dsi1_clk", CLK_SMUX2_DSI1_CLK,
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SSEL3_SELCTL1, smux2_dsi1_clk),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
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@ -452,6 +508,22 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("dsi_0_vclk1", CLK_SMUX2_DSI0_CLK, 14, 10, 7, 10,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK, 14, 11, 7, 11,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
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BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
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DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
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BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
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DEF_MOD("lcdc_0_clk_d", CLK_SMUX2_DSI0_CLK, 14, 15, 7, 15,
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BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
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DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
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@ -460,6 +532,14 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
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BUS_MSTOP(2, BIT(15))),
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DEF_MOD("dsi_0_vclk2", CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
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BUS_MSTOP(9, BIT(15) | BIT(14))),
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DEF_MOD("lcdc_1_clk_a", CLK_PLLDTY_ACPU_DIV2, 26, 8, 10, 30,
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BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
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DEF_MOD("lcdc_1_clk_p", CLK_PLLDTY_DIV16, 26, 9, 10, 31,
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BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
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DEF_MOD("lcdc_1_clk_d", CLK_SMUX2_DSI1_CLK, 26, 10, 11, 0,
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BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
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};
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static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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@ -535,10 +615,14 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
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DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
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DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
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DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
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DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
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DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
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DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
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DEF_RST(17, 14, 8, 15), /* LCDC_1_RESET_N */
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};
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const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
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@ -76,6 +76,11 @@
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/* On RZ/G3E SoC we have two DSI PLLs */
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#define MAX_CPG_DSI_PLL 2
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#define CPG_PLLDSI_SMUX_LVDS_DUTY_NUM 4
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#define CPG_PLLDSI_SMUX_LVDS_DUTY_DEN 7
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#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM 1
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#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN 2
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/**
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* struct rzv2h_pll_dsi_info - PLL DSI information, holds the limits and parameters
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*
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@ -418,6 +423,20 @@ bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
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}
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EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG");
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/**
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* struct rzv2h_plldsi_mux_clk - PLL DSI MUX clock
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*
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* @priv: CPG private data
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* @mux: mux clk
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*/
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struct rzv2h_plldsi_mux_clk {
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struct rzv2h_cpg_priv *priv;
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struct clk_mux mux;
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};
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#define to_plldsi_clk_mux(_mux) \
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container_of(_mux, struct rzv2h_plldsi_mux_clk, mux)
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static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -649,6 +668,165 @@ static int rzv2h_cpg_plldsi_set_rate(struct clk_hw *hw, unsigned long rate,
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return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);
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}
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static u8 rzv2h_cpg_plldsi_smux_get_parent(struct clk_hw *hw)
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{
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return clk_mux_ops.get_parent(hw);
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}
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static int rzv2h_cpg_plldsi_smux_set_parent(struct clk_hw *hw, u8 index)
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{
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return clk_mux_ops.set_parent(hw, index);
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}
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static int rzv2h_cpg_plldsi_smux_lvds_determine_rate(struct rzv2h_cpg_priv *priv,
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struct pll_clk *pll_clk,
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struct clk_rate_request *req)
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{
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struct rzv2h_pll_div_pars *dsi_params;
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struct rzv2h_pll_dsi_info *dsi_info;
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u8 lvds_table[] = { 7 };
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u64 rate_millihz;
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dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
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dsi_params = &dsi_info->pll_dsi_parameters;
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rate_millihz = mul_u32_u32(req->rate, MILLI);
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if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_params,
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lvds_table, ARRAY_SIZE(lvds_table), rate_millihz)) {
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dev_err(priv->dev, "failed to determine rate for req->rate: %lu\n",
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req->rate);
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return -EINVAL;
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}
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req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz, MILLI);
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req->best_parent_rate = req->rate;
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dsi_info->req_pll_dsi_rate = req->best_parent_rate * dsi_params->div.divider_value;
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return 0;
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}
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static int rzv2h_cpg_plldsi_smux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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struct rzv2h_plldsi_mux_clk *dsi_mux = to_plldsi_clk_mux(mux);
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struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));
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struct rzv2h_cpg_priv *priv = dsi_mux->priv;
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/*
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* For LVDS output (parent index 0), calculate PLL parameters with
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* fixed divider value of 7. For DSI/RGB output (parent index 1) skip
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* PLL calculation here as it's handled by determine_rate of the
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* divider (up one level).
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*/
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if (!clk_mux_ops.get_parent(hw))
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return rzv2h_cpg_plldsi_smux_lvds_determine_rate(priv, pll_clk, req);
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req->best_parent_rate = req->rate;
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return 0;
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}
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static int rzv2h_cpg_plldsi_smux_get_duty_cycle(struct clk_hw *hw,
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struct clk_duty *duty)
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{
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u8 parent = clk_mux_ops.get_parent(hw);
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/*
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* CDIV7_DSIx_CLK - LVDS path (div7) - duty 4/7.
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* CSDIV_DSIx - DSI/RGB path (csdiv) - duty 1/2.
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*/
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if (parent == 0) {
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duty->num = CPG_PLLDSI_SMUX_LVDS_DUTY_NUM;
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duty->den = CPG_PLLDSI_SMUX_LVDS_DUTY_DEN;
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} else {
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duty->num = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM;
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duty->den = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN;
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}
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return 0;
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}
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static int rzv2h_cpg_plldsi_smux_set_duty_cycle(struct clk_hw *hw,
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struct clk_duty *duty)
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{
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struct clk_hw *parent_hw;
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u8 parent_idx;
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/*
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* Select parent based on requested duty cycle:
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* - If duty > 50% (num/den > 1/2), select LVDS path (parent 0)
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* - Otherwise, select DSI/RGB path (parent 1)
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*/
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if (duty->num * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN >
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duty->den * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM)
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parent_idx = 0;
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else
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parent_idx = 1;
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if (parent_idx >= clk_hw_get_num_parents(hw))
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return -EINVAL;
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parent_hw = clk_hw_get_parent_by_index(hw, parent_idx);
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if (!parent_hw)
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return -EINVAL;
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return clk_hw_set_parent(hw, parent_hw);
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}
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static const struct clk_ops rzv2h_cpg_plldsi_smux_ops = {
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.determine_rate = rzv2h_cpg_plldsi_smux_determine_rate,
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.get_parent = rzv2h_cpg_plldsi_smux_get_parent,
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.set_parent = rzv2h_cpg_plldsi_smux_set_parent,
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.get_duty_cycle = rzv2h_cpg_plldsi_smux_get_duty_cycle,
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.set_duty_cycle = rzv2h_cpg_plldsi_smux_set_duty_cycle,
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};
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static struct clk * __init
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rzv2h_cpg_plldsi_smux_clk_register(const struct cpg_core_clk *core,
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struct rzv2h_cpg_priv *priv)
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{
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struct rzv2h_plldsi_mux_clk *clk_hw_data;
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struct clk_init_data init;
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struct clk_hw *clk_hw;
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struct smuxed smux;
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int ret;
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smux = core->cfg.smux;
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if (smux.shift + smux.width > 16) {
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dev_err(priv->dev, "mux value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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|
||||
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
|
||||
if (!clk_hw_data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_hw_data->priv = priv;
|
||||
|
||||
init.name = core->name;
|
||||
init.ops = &rzv2h_cpg_plldsi_smux_ops;
|
||||
init.flags = core->flag;
|
||||
init.parent_names = core->parent_names;
|
||||
init.num_parents = core->num_parents;
|
||||
|
||||
clk_hw_data->mux.reg = priv->base + smux.offset;
|
||||
|
||||
clk_hw_data->mux.shift = smux.shift;
|
||||
clk_hw_data->mux.mask = clk_div_mask(smux.width);
|
||||
clk_hw_data->mux.flags = core->mux_flags;
|
||||
clk_hw_data->mux.lock = &priv->rmw_lock;
|
||||
|
||||
clk_hw = &clk_hw_data->mux.hw;
|
||||
clk_hw->init = &init;
|
||||
|
||||
ret = devm_clk_hw_register(priv->dev, clk_hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
return clk_hw->clk;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
|
|
@ -1085,6 +1263,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
|
|||
case CLK_TYPE_PLLDSI_DIV:
|
||||
clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);
|
||||
break;
|
||||
case CLK_TYPE_PLLDSI_SMUX:
|
||||
clk = rzv2h_cpg_plldsi_smux_clk_register(core, priv);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -121,6 +121,7 @@ struct fixed_mod_conf {
|
|||
|
||||
#define CPG_SSEL0 (0x300)
|
||||
#define CPG_SSEL1 (0x304)
|
||||
#define CPG_SSEL3 (0x30C)
|
||||
#define CPG_CDDIV0 (0x400)
|
||||
#define CPG_CDDIV1 (0x404)
|
||||
#define CPG_CDDIV2 (0x408)
|
||||
|
|
@ -148,6 +149,7 @@ struct fixed_mod_conf {
|
|||
#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
|
||||
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
|
||||
#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
|
||||
#define CSDIV1_DIVCTL3 DDIV_PACK(CPG_CSDIV1, 12, 4, CSDIV_NO_MON)
|
||||
|
||||
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
|
||||
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
|
||||
|
|
@ -155,6 +157,8 @@ struct fixed_mod_conf {
|
|||
#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
|
||||
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
|
||||
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
|
||||
#define SSEL3_SELCTL0 SMUX_PACK(CPG_SSEL3, 0, 1)
|
||||
#define SSEL3_SELCTL1 SMUX_PACK(CPG_SSEL3, 4, 1)
|
||||
|
||||
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
|
||||
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
|
||||
|
|
@ -203,6 +207,7 @@ enum clk_types {
|
|||
CLK_TYPE_SMUX, /* Static Mux */
|
||||
CLK_TYPE_PLLDSI, /* PLLDSI */
|
||||
CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */
|
||||
CLK_TYPE_PLLDSI_SMUX, /* PLLDSI Static Mux */
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
|
|
@ -241,6 +246,13 @@ enum clk_types {
|
|||
.dtable = _dtable, \
|
||||
.parent = _parent, \
|
||||
.flag = CLK_SET_RATE_PARENT)
|
||||
#define DEF_PLLDSI_SMUX(_name, _id, _smux_packed, _parent_names) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_SMUX, \
|
||||
.cfg.smux = _smux_packed, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = ARRAY_SIZE(_parent_names), \
|
||||
.flag = CLK_SET_RATE_PARENT, \
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK)
|
||||
|
||||
/**
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
|
|
|
|||
|
|
@ -164,6 +164,26 @@ struct rzv2h_pll_div_pars {
|
|||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#define RZG3E_CPG_PLL_DSI0_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 1218 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#define RZG3E_CPG_PLL_DSI1_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 609 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#ifdef CONFIG_CLK_RZV2H
|
||||
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars, u64 freq_millihz);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user