mirror of
https://github.com/torvalds/linux.git
synced 2026-06-07 14:04:54 +02:00
Merge 8db5efb83f ("Merge tag 'pinctrl-v5.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl") into android-mainline
Steps on the way to 5.12-final. Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I69f5e15ec5fc7d321b4fe77c6dd8e6a38adf61ec
This commit is contained in:
Greg Kroah-Hartman
commit
6ecf1ebff1
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|
@ -21,5 +21,5 @@ led {
|
|||
};
|
||||
|
||||
&mmc0 {
|
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 push-push switch */
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broken-cd; /* card detect is broken on *some* boards */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ / {
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|||
model = "NVIDIA Jetson TX2 Developer Kit";
|
||||
compatible = "nvidia,p2771-0000", "nvidia,tegra186";
|
||||
|
||||
aconnect {
|
||||
aconnect@2900000 {
|
||||
status = "okay";
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||||
|
||||
dma-controller@2930000 {
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||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ aliases {
|
|||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon console=ttyS0,115200n8";
|
||||
bootargs = "earlycon console=ttyS0,115200n8 fw_devlink=on";
|
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stdout-path = "serial0:115200n8";
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};
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|
|
|
|||
|
|
@ -73,7 +73,7 @@ ethernet@2490000 {
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|||
snps,rxpbl = <8>;
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};
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aconnect {
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aconnect@2900000 {
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||||
compatible = "nvidia,tegra186-aconnect",
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"nvidia,tegra210-aconnect";
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clocks = <&bpmp TEGRA186_CLK_APE>,
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|
|
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|||
|
|
@ -651,6 +651,8 @@ rt5658: audio-codec@1a {
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reg = <0x1a>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
|
||||
clock-names = "mclk";
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realtek,jd-src = <2>;
|
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sound-name-prefix = "CVB-RT";
|
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|
||||
|
|
@ -658,7 +660,6 @@ port {
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rt5658_ep: endpoint {
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remote-endpoint = <&i2s1_dap_ep>;
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mclk-fs = <256>;
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clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
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};
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};
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};
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|
|
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|||
|
|
@ -5,6 +5,10 @@ / {
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|||
model = "NVIDIA Jetson Xavier NX (SD-card)";
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compatible = "nvidia,p3668-0000", "nvidia,tegra194";
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|
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aliases {
|
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mmc0 = "/bus@0/mmc@3400000";
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||||
};
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|
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bus@0 {
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/* SDMMC1 (SD/MMC) */
|
||||
mmc@3400000 {
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||||
|
|
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|||
|
|
@ -5,6 +5,10 @@ / {
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|||
model = "NVIDIA Jetson Xavier NX (eMMC)";
|
||||
compatible = "nvidia,p3668-0001", "nvidia,tegra194";
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|
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aliases {
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mmc0 = "/bus@0/mmc@3460000";
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};
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bus@0 {
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/* SDMMC4 (eMMC) */
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mmc@3460000 {
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|
|
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|
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@ -14,7 +14,6 @@ aliases {
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i2c5 = "/bus@0/i2c@31c0000";
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i2c6 = "/bus@0/i2c@c250000";
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i2c7 = "/bus@0/i2c@31e0000";
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mmc0 = "/bus@0/mmc@3460000";
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rtc0 = "/bpmp/i2c/pmic@3c";
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rtc1 = "/bus@0/rtc@c2a0000";
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serial0 = &tcu;
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|
|
|
|||
|
|
@ -89,6 +89,8 @@ static int blkdev_reread_part(struct block_device *bdev, fmode_t mode)
|
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return -EINVAL;
|
||||
if (!capable(CAP_SYS_ADMIN))
|
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return -EACCES;
|
||||
if (bdev->bd_part_count)
|
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return -EBUSY;
|
||||
|
||||
/*
|
||||
* Reopen the device to revalidate the driver state and force a
|
||||
|
|
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|||
|
|
@ -29,6 +29,7 @@
|
|||
#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
|
||||
|
||||
struct gpio_regs {
|
||||
u32 sysconfig;
|
||||
u32 irqenable1;
|
||||
u32 irqenable2;
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||||
u32 wake_en;
|
||||
|
|
@ -1069,6 +1070,7 @@ static void omap_gpio_init_context(struct gpio_bank *p)
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const struct omap_gpio_reg_offs *regs = p->regs;
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void __iomem *base = p->base;
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|
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p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
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p->context.ctrl = readl_relaxed(base + regs->ctrl);
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p->context.oe = readl_relaxed(base + regs->direction);
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p->context.wake_en = readl_relaxed(base + regs->wkup_en);
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|
|
@ -1088,6 +1090,7 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
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const struct omap_gpio_reg_offs *regs = bank->regs;
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void __iomem *base = bank->base;
|
||||
|
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writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
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||||
writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
|
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writel_relaxed(bank->context.ctrl, base + regs->ctrl);
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writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
|
||||
|
|
@ -1115,6 +1118,10 @@ static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
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|
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bank->saved_datain = readl_relaxed(base + bank->regs->datain);
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||||
|
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/* Save syconfig, it's runtime value can be different from init value */
|
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if (bank->loses_context)
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bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
|
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|
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if (!bank->enabled_non_wakeup_gpios)
|
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goto update_gpio_context_count;
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|
||||
|
|
@ -1279,6 +1286,7 @@ static int gpio_omap_cpu_notifier(struct notifier_block *nb,
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|
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static const struct omap_gpio_reg_offs omap2_gpio_regs = {
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.revision = OMAP24XX_GPIO_REVISION,
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.sysconfig = OMAP24XX_GPIO_SYSCONFIG,
|
||||
.direction = OMAP24XX_GPIO_OE,
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.datain = OMAP24XX_GPIO_DATAIN,
|
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.dataout = OMAP24XX_GPIO_DATAOUT,
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||||
|
|
@ -1302,6 +1310,7 @@ static const struct omap_gpio_reg_offs omap2_gpio_regs = {
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|
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static const struct omap_gpio_reg_offs omap4_gpio_regs = {
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.revision = OMAP4_GPIO_REVISION,
|
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.sysconfig = OMAP4_GPIO_SYSCONFIG,
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.direction = OMAP4_GPIO_OE,
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.datain = OMAP4_GPIO_DATAIN,
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.dataout = OMAP4_GPIO_DATAOUT,
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||||
|
|
|
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|
|
@ -3300,7 +3300,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
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struct amdgpu_bo *root;
|
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uint64_t value, flags;
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struct amdgpu_vm *vm;
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||||
long r;
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int r;
|
||||
|
||||
spin_lock(&adev->vm_manager.pasid_lock);
|
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vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
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|
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@ -3349,6 +3349,12 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
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value = 0;
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||||
}
|
||||
|
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r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
|
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if (r) {
|
||||
pr_debug("failed %d to reserve fence slot\n", r);
|
||||
goto error_unlock;
|
||||
}
|
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|
||||
r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
|
||||
addr, flags, value, NULL, NULL,
|
||||
NULL);
|
||||
|
|
@ -3360,7 +3366,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
|
|||
error_unlock:
|
||||
amdgpu_bo_unreserve(root);
|
||||
if (r < 0)
|
||||
DRM_ERROR("Can't handle page fault (%ld)\n", r);
|
||||
DRM_ERROR("Can't handle page fault (%d)\n", r);
|
||||
|
||||
error_unref:
|
||||
amdgpu_bo_unref(&root);
|
||||
|
|
|
|||
|
|
@ -3280,7 +3280,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
|
|||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
|
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
|
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
|
||||
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
|
||||
|
|
|
|||
|
|
@ -4071,13 +4071,6 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
|
|||
if (modifier == DRM_FORMAT_MOD_LINEAR)
|
||||
return true;
|
||||
|
||||
/*
|
||||
* The arbitrary tiling support for multiplane formats has not been hooked
|
||||
* up.
|
||||
*/
|
||||
if (info->num_planes > 1)
|
||||
return false;
|
||||
|
||||
/*
|
||||
* For D swizzle the canonical modifier depends on the bpp, so check
|
||||
* it here.
|
||||
|
|
@ -4096,6 +4089,10 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
|
|||
/* Per radeonsi comments 16/64 bpp are more complicated. */
|
||||
if (info->cpp[0] != 4)
|
||||
return false;
|
||||
/* We support multi-planar formats, but not when combined with
|
||||
* additional DCC metadata planes. */
|
||||
if (info->num_planes > 1)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
@ -4296,7 +4293,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
|
|||
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
|
||||
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
|
||||
|
||||
add_modifier(mods, size, capacity, AMD_FMT_MOD |
|
||||
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
|
||||
|
|
@ -4308,7 +4305,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
|
|||
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
|
||||
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
|
||||
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
|
||||
|
||||
add_modifier(mods, size, capacity, AMD_FMT_MOD |
|
||||
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
|
||||
|
|
|
|||
|
|
@ -848,7 +848,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
|
|||
int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
|
||||
|
||||
if (lttpr_count < 0)
|
||||
return;
|
||||
/* Still continue with enabling the port and link training. */
|
||||
lttpr_count = 0;
|
||||
|
||||
if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
|
||||
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
|
||||
|
|
|
|||
|
|
@ -916,19 +916,26 @@ static int cmd_reg_handler(struct parser_exec_state *s,
|
|||
|
||||
if (!strncmp(cmd, "srm", 3) ||
|
||||
!strncmp(cmd, "lrm", 3)) {
|
||||
if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
|
||||
offset != 0x21f0) {
|
||||
if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
|
||||
offset == 0x21f0 ||
|
||||
(IS_BROADWELL(gvt->gt->i915) &&
|
||||
offset == i915_mmio_reg_offset(INSTPM)))
|
||||
return 0;
|
||||
else {
|
||||
gvt_vgpu_err("%s access to register (%x)\n",
|
||||
cmd, offset);
|
||||
return -EPERM;
|
||||
} else
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (!strncmp(cmd, "lrr-src", 7) ||
|
||||
!strncmp(cmd, "lrr-dst", 7)) {
|
||||
gvt_vgpu_err("not allowed cmd %s\n", cmd);
|
||||
return -EPERM;
|
||||
if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
|
||||
return 0;
|
||||
else {
|
||||
gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
|
||||
return -EPERM;
|
||||
}
|
||||
}
|
||||
|
||||
if (!strncmp(cmd, "pipe_ctrl", 9)) {
|
||||
|
|
|
|||
|
|
@ -1604,8 +1604,8 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
|
|||
unsigned i, pin;
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
struct pinctrl_gpio_range *range;
|
||||
unsigned int gpio_num;
|
||||
struct gpio_chip *chip;
|
||||
int gpio_num;
|
||||
#endif
|
||||
|
||||
seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
|
||||
|
|
@ -1625,7 +1625,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
|
|||
seq_printf(s, "pin %d (%s) ", pin, desc->name);
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
gpio_num = 0;
|
||||
gpio_num = -1;
|
||||
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
|
||||
if ((pin >= range->pin_base) &&
|
||||
(pin < (range->pin_base + range->npins))) {
|
||||
|
|
@ -1633,10 +1633,12 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
|
|||
break;
|
||||
}
|
||||
}
|
||||
chip = gpio_to_chip(gpio_num);
|
||||
if (chip && chip->gpiodev && chip->gpiodev->base)
|
||||
seq_printf(s, "%u:%s ", gpio_num -
|
||||
chip->gpiodev->base, chip->label);
|
||||
if (gpio_num >= 0)
|
||||
chip = gpio_to_chip(gpio_num);
|
||||
else
|
||||
chip = NULL;
|
||||
if (chip)
|
||||
seq_printf(s, "%u:%s ", gpio_num - chip->gpiodev->base, chip->label);
|
||||
else
|
||||
seq_puts(s, "0:? ");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -299,9 +299,9 @@ static const struct pinctrl_pin_desc lbg_pins[] = {
|
|||
static const struct intel_community lbg_communities[] = {
|
||||
LBG_COMMUNITY(0, 0, 71),
|
||||
LBG_COMMUNITY(1, 72, 132),
|
||||
LBG_COMMUNITY(3, 133, 144),
|
||||
LBG_COMMUNITY(4, 145, 180),
|
||||
LBG_COMMUNITY(5, 181, 246),
|
||||
LBG_COMMUNITY(3, 133, 143),
|
||||
LBG_COMMUNITY(4, 144, 178),
|
||||
LBG_COMMUNITY(5, 179, 246),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data lbg_soc_data = {
|
||||
|
|
|
|||
|
|
@ -175,10 +175,10 @@ coda_file_mmap(struct file *coda_file, struct vm_area_struct *vma)
|
|||
ret = call_mmap(vma->vm_file, vma);
|
||||
|
||||
if (ret) {
|
||||
/* if call_mmap fails, our caller will put coda_file so we
|
||||
* should drop the reference to the host_file that we got.
|
||||
/* if call_mmap fails, our caller will put host_file so we
|
||||
* should drop the reference to the coda_file that we got.
|
||||
*/
|
||||
fput(host_file);
|
||||
fput(coda_file);
|
||||
kfree(cvm_ops);
|
||||
} else {
|
||||
/* here we add redirects for the open/close vm_operations */
|
||||
|
|
|
|||
|
|
@ -417,20 +417,11 @@ static int ovl_mmap(struct file *file, struct vm_area_struct *vma)
|
|||
if (WARN_ON(file != vma->vm_file))
|
||||
return -EIO;
|
||||
|
||||
vma->vm_file = get_file(realfile);
|
||||
vma_set_file(vma, realfile);
|
||||
|
||||
old_cred = ovl_override_creds(file_inode(file)->i_sb);
|
||||
ret = call_mmap(vma->vm_file, vma);
|
||||
revert_creds(old_cred);
|
||||
|
||||
if (ret) {
|
||||
/* Drop reference count from new vm_file value */
|
||||
fput(realfile);
|
||||
} else {
|
||||
/* Drop reference count from previous vm_file value */
|
||||
fput(file);
|
||||
}
|
||||
|
||||
ovl_file_accessed(file);
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@
|
|||
* omap2+ specific GPIO registers
|
||||
*/
|
||||
#define OMAP24XX_GPIO_REVISION 0x0000
|
||||
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
|
||||
#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
|
||||
#define OMAP24XX_GPIO_IRQENABLE2 0x002c
|
||||
|
|
@ -108,6 +109,7 @@
|
|||
#define OMAP24XX_GPIO_SETDATAOUT 0x0094
|
||||
|
||||
#define OMAP4_GPIO_REVISION 0x0000
|
||||
#define OMAP4_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP4_GPIO_EOI 0x0020
|
||||
#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
|
||||
#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
|
||||
|
|
@ -148,6 +150,7 @@
|
|||
#ifndef __ASSEMBLER__
|
||||
struct omap_gpio_reg_offs {
|
||||
u16 revision;
|
||||
u16 sysconfig;
|
||||
u16 direction;
|
||||
u16 datain;
|
||||
u16 dataout;
|
||||
|
|
|
|||
31
mm/filemap.c
31
mm/filemap.c
|
|
@ -1969,8 +1969,14 @@ unsigned find_lock_entries(struct address_space *mapping, pgoff_t start,
|
|||
put:
|
||||
put_page(page);
|
||||
next:
|
||||
if (!xa_is_value(page) && PageTransHuge(page))
|
||||
xas_set(&xas, page->index + thp_nr_pages(page));
|
||||
if (!xa_is_value(page) && PageTransHuge(page)) {
|
||||
unsigned int nr_pages = thp_nr_pages(page);
|
||||
|
||||
/* Final THP may cross MAX_LFS_FILESIZE on 32-bit */
|
||||
xas_set(&xas, page->index + nr_pages);
|
||||
if (xas.xa_index < nr_pages)
|
||||
break;
|
||||
}
|
||||
}
|
||||
rcu_read_unlock();
|
||||
|
||||
|
|
@ -2672,7 +2678,7 @@ loff_t mapping_seek_hole_data(struct address_space *mapping, loff_t start,
|
|||
loff_t end, int whence)
|
||||
{
|
||||
XA_STATE(xas, &mapping->i_pages, start >> PAGE_SHIFT);
|
||||
pgoff_t max = (end - 1) / PAGE_SIZE;
|
||||
pgoff_t max = (end - 1) >> PAGE_SHIFT;
|
||||
bool seek_data = (whence == SEEK_DATA);
|
||||
struct page *page;
|
||||
|
||||
|
|
@ -2681,7 +2687,8 @@ loff_t mapping_seek_hole_data(struct address_space *mapping, loff_t start,
|
|||
|
||||
rcu_read_lock();
|
||||
while ((page = find_get_entry(&xas, max, XA_PRESENT))) {
|
||||
loff_t pos = xas.xa_index * PAGE_SIZE;
|
||||
loff_t pos = (u64)xas.xa_index << PAGE_SHIFT;
|
||||
unsigned int seek_size;
|
||||
|
||||
if (start < pos) {
|
||||
if (!seek_data)
|
||||
|
|
@ -2689,25 +2696,25 @@ loff_t mapping_seek_hole_data(struct address_space *mapping, loff_t start,
|
|||
start = pos;
|
||||
}
|
||||
|
||||
pos += seek_page_size(&xas, page);
|
||||
seek_size = seek_page_size(&xas, page);
|
||||
pos = round_up(pos + 1, seek_size);
|
||||
start = page_seek_hole_data(&xas, mapping, page, start, pos,
|
||||
seek_data);
|
||||
if (start < pos)
|
||||
goto unlock;
|
||||
if (start >= end)
|
||||
break;
|
||||
if (seek_size > PAGE_SIZE)
|
||||
xas_set(&xas, pos >> PAGE_SHIFT);
|
||||
if (!xa_is_value(page))
|
||||
put_page(page);
|
||||
}
|
||||
rcu_read_unlock();
|
||||
|
||||
if (seek_data)
|
||||
return -ENXIO;
|
||||
goto out;
|
||||
|
||||
start = -ENXIO;
|
||||
unlock:
|
||||
rcu_read_unlock();
|
||||
if (!xa_is_value(page))
|
||||
if (page && !xa_is_value(page))
|
||||
put_page(page);
|
||||
out:
|
||||
if (start > end)
|
||||
return end;
|
||||
return start;
|
||||
|
|
|
|||
|
|
@ -128,9 +128,9 @@ def detect_kernel_config():
|
|||
|
||||
cfg['nr_nodes'] = prog['nr_online_nodes'].value_()
|
||||
|
||||
if prog.type('struct kmem_cache').members[1][1] == 'flags':
|
||||
if prog.type('struct kmem_cache').members[1].name == 'flags':
|
||||
cfg['allocator'] = 'SLUB'
|
||||
elif prog.type('struct kmem_cache').members[1][1] == 'batchcount':
|
||||
elif prog.type('struct kmem_cache').members[1].name == 'batchcount':
|
||||
cfg['allocator'] = 'SLAB'
|
||||
else:
|
||||
err('Can\'t determine the slab allocator')
|
||||
|
|
@ -193,7 +193,7 @@ def main():
|
|||
# look over all slab pages, belonging to non-root memcgs
|
||||
# and look for objects belonging to the given memory cgroup
|
||||
for page in for_each_slab_page(prog):
|
||||
objcg_vec_raw = page.obj_cgroups.value_()
|
||||
objcg_vec_raw = page.memcg_data.value_()
|
||||
if objcg_vec_raw == 0:
|
||||
continue
|
||||
cache = page.slab_cache
|
||||
|
|
@ -202,7 +202,7 @@ def main():
|
|||
addr = cache.value_()
|
||||
caches[addr] = cache
|
||||
# clear the lowest bit to get the true obj_cgroups
|
||||
objcg_vec = Object(prog, page.obj_cgroups.type_,
|
||||
objcg_vec = Object(prog, 'struct obj_cgroup **',
|
||||
value=objcg_vec_raw & ~1)
|
||||
|
||||
if addr not in stats:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user