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- Avoid lock inversion when pinning to GGTT on CHV/BXT+VTD (Janusz)

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- Fix conversion between clock ticks and nanoseconds (Umesh)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmkMsMoACgkQ+mJfZA7r
 E8p+KwgAjyO+Dm1VhWgvkOhlLBUavLOhilYoCtGDp3uXkLPnuyyLOsKSX7kRrNaM
 Zt8Z+624QP7aw096Ek4DfRGY5y74dlc4egmzO7OoRolPMai/GRV6rz/8XZg6zALp
 4NvHWWdawQUZz82rcc+gAU5Ugbe2r7MTZMgyiyB75BzDj536U5rEur6v1JsheJvB
 gx6WuPWYYKB4e+IwSdhKPIV5kzhUdJ7npV5CWTOhwTAwsHuX/lljrYJh9il5OOLM
 Drz3KiDpJ8OwrwkFYFUBJ3+QNQdRCZN+bMo7RBlU8eQB4ZU9RL5cr77g0BtMDKVY
 Xu1ieB0ZocvrRfNZ/67K0aLh7Z837g==
 =cQMw
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-fixes-2025-11-06' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes

- Avoid lock inversion when pinning to GGTT on CHV/BXT+VTD (Janusz)
- Fix conversion between clock ticks and nanoseconds (Umesh)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/aQyxT1D8IW-xcDbM@intel.com
This commit is contained in:
Dave Airlie 2025-11-07 09:14:55 +10:00
commit 6ec8a47c55
2 changed files with 16 additions and 4 deletions
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4
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
View File

@ -205,7 +205,7 @@ static u64 div_u64_roundup(u64 nom, u32 den)
u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count)
{
return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency);
return mul_u64_u32_div(count, NSEC_PER_SEC, gt->clock_frequency);
}
u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count)
@ -215,7 +215,7 @@ u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count)
u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns)
{
return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC);
return mul_u64_u32_div(ns, gt->clock_frequency, NSEC_PER_SEC);
}
u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)

16
drivers/gpu/drm/i915/i915_vma.c
View File

@ -1595,8 +1595,20 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
err_vma_res:
i915_vma_resource_free(vma_res);
err_fence:
if (work)
dma_fence_work_commit_imm(&work->base);
if (work) {
/*
* When pinning VMA to GGTT on CHV or BXT with VTD enabled,
* commit VMA binding asynchronously to avoid risk of lock
* inversion among reservation_ww locks held here and
* cpu_hotplug_lock acquired from stop_machine(), which we
* wrap around GGTT updates when running in those environments.
*/
if (i915_vma_is_ggtt(vma) &&
intel_vm_no_concurrent_access_wa(vma->vm->i915))
dma_fence_work_commit(&work->base);
else
dma_fence_work_commit_imm(&work->base);
}
err_rpm:
intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref);