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drm/i915: Separate VRR related register definitions
Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-3-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani
Suraj Kandpal
parent
fc8fc81cb8
commit
6eb8276188
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@ -9,6 +9,7 @@
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_vrr.h"
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#include "intel_vrr_regs.h"
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#include "intel_dp.h"
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bool intel_vrr_is_capable(struct intel_connector *connector)
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111
drivers/gpu/drm/i915/display/intel_vrr_regs.h
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111
drivers/gpu/drm/i915/display/intel_vrr_regs.h
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@ -0,0 +1,111 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef __INTEL_VRR_REGS_H__
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#define __INTEL_VRR_REGS_H__
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#include "intel_display_reg_defs.h"
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/* VRR registers */
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#define _TRANS_VRR_CTL_A 0x60420
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#define _TRANS_VRR_CTL_B 0x61420
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#define _TRANS_VRR_CTL_C 0x62420
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#define _TRANS_VRR_CTL_D 0x63420
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#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
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#define VRR_CTL_VRR_ENABLE REG_BIT(31)
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#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
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#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
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#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
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#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
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#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
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#define _TRANS_VRR_VMAX_A 0x60424
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#define _TRANS_VRR_VMAX_B 0x61424
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#define _TRANS_VRR_VMAX_C 0x62424
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#define _TRANS_VRR_VMAX_D 0x63424
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#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
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#define VRR_VMAX_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_VMIN_A 0x60434
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#define _TRANS_VRR_VMIN_B 0x61434
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#define _TRANS_VRR_VMIN_C 0x62434
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#define _TRANS_VRR_VMIN_D 0x63434
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#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
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#define VRR_VMIN_MASK REG_GENMASK(15, 0)
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#define _TRANS_VRR_VMAXSHIFT_A 0x60428
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#define _TRANS_VRR_VMAXSHIFT_B 0x61428
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#define _TRANS_VRR_VMAXSHIFT_C 0x62428
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#define _TRANS_VRR_VMAXSHIFT_D 0x63428
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#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_VMAXSHIFT_A)
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#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
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#define VRR_VMAXSHIFT_DEC REG_BIT(16)
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#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
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#define _TRANS_VRR_STATUS_A 0x6042c
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#define _TRANS_VRR_STATUS_B 0x6142c
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#define _TRANS_VRR_STATUS_C 0x6242c
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#define _TRANS_VRR_STATUS_D 0x6342c
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#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
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#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
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#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
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#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
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#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
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#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
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#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
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#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
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#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
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#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
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#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
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#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
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#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
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#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
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#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
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#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
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#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
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#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
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#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
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#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_VTOTAL_PREV_A)
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#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
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#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
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#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
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#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_FLIPLINE_A 0x60438
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#define _TRANS_VRR_FLIPLINE_B 0x61438
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#define _TRANS_VRR_FLIPLINE_C 0x62438
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#define _TRANS_VRR_FLIPLINE_D 0x63438
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#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_FLIPLINE_A)
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#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_STATUS2_A 0x6043c
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#define _TRANS_VRR_STATUS2_B 0x6143c
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#define _TRANS_VRR_STATUS2_C 0x6243c
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#define _TRANS_VRR_STATUS2_D 0x6343c
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#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
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#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
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#define _TRANS_PUSH_A 0x60a70
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#define _TRANS_PUSH_B 0x61a70
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#define _TRANS_PUSH_C 0x62a70
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#define _TRANS_PUSH_D 0x63a70
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#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
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#define TRANS_PUSH_EN REG_BIT(31)
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#define TRANS_PUSH_SEND REG_BIT(30)
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#define _TRANS_VRR_VSYNC_A 0x60078
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#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
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#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
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#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
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#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
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#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
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#endif /* __INTEL_VRR_REGS__ */
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@ -1147,106 +1147,6 @@
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#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
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#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
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/* VRR registers */
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#define _TRANS_VRR_CTL_A 0x60420
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#define _TRANS_VRR_CTL_B 0x61420
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#define _TRANS_VRR_CTL_C 0x62420
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#define _TRANS_VRR_CTL_D 0x63420
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#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
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#define VRR_CTL_VRR_ENABLE REG_BIT(31)
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#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
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#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
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#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
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#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
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#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
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#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
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#define _TRANS_VRR_VMAX_A 0x60424
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#define _TRANS_VRR_VMAX_B 0x61424
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#define _TRANS_VRR_VMAX_C 0x62424
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#define _TRANS_VRR_VMAX_D 0x63424
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#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
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#define VRR_VMAX_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_VMIN_A 0x60434
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#define _TRANS_VRR_VMIN_B 0x61434
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#define _TRANS_VRR_VMIN_C 0x62434
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#define _TRANS_VRR_VMIN_D 0x63434
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#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
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#define VRR_VMIN_MASK REG_GENMASK(15, 0)
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#define _TRANS_VRR_VMAXSHIFT_A 0x60428
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#define _TRANS_VRR_VMAXSHIFT_B 0x61428
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#define _TRANS_VRR_VMAXSHIFT_C 0x62428
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#define _TRANS_VRR_VMAXSHIFT_D 0x63428
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#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_VMAXSHIFT_A)
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#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
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#define VRR_VMAXSHIFT_DEC REG_BIT(16)
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#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
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#define _TRANS_VRR_STATUS_A 0x6042c
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#define _TRANS_VRR_STATUS_B 0x6142c
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#define _TRANS_VRR_STATUS_C 0x6242c
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#define _TRANS_VRR_STATUS_D 0x6342c
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#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
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#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
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#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
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#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
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#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
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#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
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#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
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#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
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#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
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#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
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#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
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#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
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#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
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#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
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#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
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#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
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#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
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#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
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#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
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#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_VTOTAL_PREV_A)
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#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
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#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
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#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
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#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_FLIPLINE_A 0x60438
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#define _TRANS_VRR_FLIPLINE_B 0x61438
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#define _TRANS_VRR_FLIPLINE_C 0x62438
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#define _TRANS_VRR_FLIPLINE_D 0x63438
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#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
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_TRANS_VRR_FLIPLINE_A)
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#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
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#define _TRANS_VRR_STATUS2_A 0x6043c
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#define _TRANS_VRR_STATUS2_B 0x6143c
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#define _TRANS_VRR_STATUS2_C 0x6243c
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#define _TRANS_VRR_STATUS2_D 0x6343c
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#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
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#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
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#define _TRANS_PUSH_A 0x60a70
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#define _TRANS_PUSH_B 0x61a70
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#define _TRANS_PUSH_C 0x62a70
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#define _TRANS_PUSH_D 0x63a70
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#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
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#define TRANS_PUSH_EN REG_BIT(31)
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#define TRANS_PUSH_SEND REG_BIT(30)
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#define _TRANS_VRR_VSYNC_A 0x60078
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#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
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#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
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#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
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#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
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#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
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/* VGA port control */
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#define ADPA _MMIO(0x61100)
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#define PCH_ADPA _MMIO(0xe1100)
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