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clk: renesas: r8a779h0: Add watchdog clock

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Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
This commit is contained in:
Cong Dang 2024-02-01 13:21:55 +01:00 committed by Geert Uytterhoeven
parent 62527c9d46
commit 6e8b1dcb09
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/renesas/r8a779h0-cpg-mssr.c
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@ -177,6 +177,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),