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Merge "spmi: pmic-arb: add support for HW version 7"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
6e8751ae53
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@ -1,8 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
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*/
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/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */
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#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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@ -13,17 +13,26 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spmi.h>
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#include <linux/string.h>
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#include <linux/soc/qcom/spmi-pmic-arb.h>
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/* PMIC Arbiter configuration registers */
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#define PMIC_ARB_VERSION 0x0000
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#define PMIC_ARB_VERSION_V2_MIN 0x20010000
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#define PMIC_ARB_VERSION_V3_MIN 0x30000000
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#define PMIC_ARB_VERSION_V5_MIN 0x50000000
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#define PMIC_ARB_VERSION_V7_MIN 0x70000000
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#define PMIC_ARB_INT_EN 0x0004
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#define PMIC_ARB_FEATURES 0x0004
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#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
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#define PMIC_ARB_FEATURES1 0x0008
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/* PMIC Arbiter channel registers offsets */
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#define PMIC_ARB_CMD 0x00
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#define PMIC_ARB_CONFIG 0x04
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@ -48,7 +57,6 @@
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#define INVALID_EE 0xFF
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/* Ownership Table */
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#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
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#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
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/* Channel Status fields */
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@ -91,7 +99,8 @@ enum pmic_arb_channel {
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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS 512
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#define PMIC_ARB_TIMEOUT_US 100
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#define PMIC_ARB_MAX_PERIPHS_V7 1024
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#define PMIC_ARB_TIMEOUT_US 1000
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#define PMIC_ARB_MAX_TRANS_BYTES (8)
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#define PMIC_ARB_APID_MASK 0xFF
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@ -104,12 +113,12 @@ enum pmic_arb_channel {
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((((slave_id) & 0xF) << 28) | \
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(((periph_id) & 0xFF) << 20) | \
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(((irq_id) & 0x7) << 16) | \
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(((apid) & 0x1FF) << 0))
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(((apid) & 0x3FF) << 0))
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#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
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#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
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#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
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#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
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#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
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struct pmic_arb_ver_ops;
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@ -124,23 +133,36 @@ struct apid_data {
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*
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* @rd_base: on v1 "core", on v2 "observer" register base off DT.
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* @wr_base: on v1 "core", on v2 "chnls" register base off DT.
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* @wr_base_phys: Base physical address of the register range used for
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* SPMI write commands.
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* @intr: address of the SPMI interrupt control registers.
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* @cnfg: address of the PMIC Arbiter configuration registers.
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* @lock: lock to synchronize accesses.
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* @channel: execution environment channel to use for accesses.
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* @irq: PMIC ARB interrupt.
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* @ee: the current Execution Environment
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* @bus_instance: on v7: 0 = primary SPMI bus, 1 = secondary SPMI bus
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* @min_apid: minimum APID (used for bounding IRQ search)
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* @max_apid: maximum APID
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* @base_apid: on v7: minimum APID associated with the particular SPMI
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* bus instance
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* @apid_count: on v5 and v7: number of APIDs associated with the
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* particular SPMI bus instance
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @domain: irq domain object for PMIC IRQ domain
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* @spmic: SPMI controller object
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* @ver_ops: version dependent operations.
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* @ppid_to_apid in-memory copy of PPID -> APID mapping table.
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* @ppid_to_apid: in-memory copy of PPID -> APID mapping table.
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* @last_apid: Highest value APID in use
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* @apid_data: Table of data for all APIDs
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* @max_periphs: Number of elements in apid_data[]
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* @debugfs: debugfs directory pointer
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* @debug_spmi_addr: SPMI address used for debugfs operations
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*/
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struct spmi_pmic_arb {
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void __iomem *rd_base;
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void __iomem *wr_base;
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phys_addr_t wr_base_phys;
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void __iomem *intr;
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void __iomem *cnfg;
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void __iomem *core;
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@ -149,8 +171,11 @@ struct spmi_pmic_arb {
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u8 channel;
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int irq;
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u8 ee;
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u32 bus_instance;
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u16 min_apid;
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u16 max_apid;
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u16 base_apid;
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int apid_count;
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u32 *mapping_table;
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DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
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struct irq_domain *domain;
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@ -158,7 +183,10 @@ struct spmi_pmic_arb {
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const struct pmic_arb_ver_ops *ver_ops;
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u16 *ppid_to_apid;
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u16 last_apid;
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struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
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struct apid_data *apid_data;
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int max_periphs;
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struct dentry *debugfs;
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u32 debug_spmi_addr;
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};
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/**
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@ -180,6 +208,10 @@ struct spmi_pmic_arb {
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* @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
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* on v2 address of SPMI_PIC_IRQ_CLEARn.
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* @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
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* @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG
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* @wr_addr_map: maps from an SPMI address to the physical address
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* range of the registers used to perform an SPMI write
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* command to the SPMI address.
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*/
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struct pmic_arb_ver_ops {
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const char *ver_str;
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@ -196,6 +228,9 @@ struct pmic_arb_ver_ops {
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void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
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void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
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u32 (*apid_map_offset)(u16 n);
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void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n);
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int (*wr_addr_map)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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struct resource *res_out);
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};
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static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
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@ -590,17 +625,9 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
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u8 per = ppid & 0xFF;
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u8 irq_mask = BIT(id);
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dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
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__func__, apid, sid, per, id);
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writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
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if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
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(per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
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dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
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irq_mask, ppid);
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if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
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(per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
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dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
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irq_mask, ppid);
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}
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static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
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@ -631,19 +658,36 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int first = pmic_arb->min_apid >> 5;
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int last = pmic_arb->max_apid >> 5;
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/*
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* acc_offset will be non-zero for the secondary SPMI bus instance on
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* v7 controllers.
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*/
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int acc_offset = pmic_arb->base_apid >> 5;
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u8 ee = pmic_arb->ee;
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u32 status, enable;
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int i, id, apid;
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/* status based dispatch */
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bool acc_valid = false;
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u32 irq_status = 0;
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chained_irq_enter(chip, desc);
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for (i = first; i <= last; ++i) {
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status = readl_relaxed(
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ver_ops->owner_acc_status(pmic_arb, ee, i));
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status = readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee,
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i - acc_offset));
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if (status)
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acc_valid = true;
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while (status) {
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id = ffs(status) - 1;
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status &= ~BIT(id);
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apid = id + i * 32;
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if (apid < pmic_arb->min_apid
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|| apid > pmic_arb->max_apid) {
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WARN_ONCE(true, "spurious spmi irq received for apid=%d\n",
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apid);
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continue;
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}
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enable = readl_relaxed(
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ver_ops->acc_enable(pmic_arb, apid));
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if (enable & SPMI_PIC_ACC_ENABLE_BIT)
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@ -651,6 +695,28 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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}
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}
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/* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */
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if (!acc_valid) {
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for (i = pmic_arb->min_apid; i <= pmic_arb->max_apid; i++) {
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/* skip if APPS is not irq owner */
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if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee)
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continue;
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irq_status = readl_relaxed(
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ver_ops->irq_status(pmic_arb, i));
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if (irq_status) {
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enable = readl_relaxed(
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ver_ops->acc_enable(pmic_arb, i));
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if (enable & SPMI_PIC_ACC_ENABLE_BIT) {
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dev_dbg(&pmic_arb->spmic->dev,
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"Dispatching IRQ for apid=%d status=%x\n",
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i, irq_status);
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periph_interrupt(pmic_arb, i);
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}
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}
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}
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}
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chained_irq_exit(chip, desc);
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}
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@ -770,6 +836,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain,
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u16 apid = hwirq_to_apid(d->hwirq);
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u16 sid = hwirq_to_sid(d->hwirq);
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u16 irq = hwirq_to_irq(d->hwirq);
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u8 buf;
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if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
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dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
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@ -778,6 +845,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain,
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return -ENODEV;
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}
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buf = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
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return 0;
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}
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@ -933,6 +1004,21 @@ static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
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return 0x800 + 0x80 * pmic_arb->channel;
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}
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static int pmic_arb_wr_addr_map_v1(struct spmi_pmic_arb *pmic_arb, u8 sid,
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u16 addr, struct resource *res_out)
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{
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int rc;
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rc = pmic_arb_offset_v1(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
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if (rc < 0)
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return rc;
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res_out->start = pmic_arb->wr_base_phys + rc;
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res_out->end = res_out->start + 0x80 - 1;
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return 0;
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}
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static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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{
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struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
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@ -944,8 +1030,8 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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if (offset >= pmic_arb->core_size)
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break;
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regval = readl_relaxed(pmic_arb->cnfg +
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SPMI_OWNERSHIP_TABLE_REG(apid));
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regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
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apid));
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apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
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apidd->write_ee = apidd->irq_ee;
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@ -981,20 +1067,30 @@ static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
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static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
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{
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struct apid_data *apidd = pmic_arb->apid_data;
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struct apid_data *apidd;
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struct apid_data *prev_apidd;
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u16 i, apid, ppid;
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u16 i, apid, ppid, apid_max;
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bool valid, is_irq_ee;
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u32 regval, offset;
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/*
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* In order to allow multiple EEs to write to a single PPID in arbiter
|
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* version 5, there is more than one APID mapped to each PPID.
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* version 5 and 7, there is more than one APID mapped to each PPID.
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* The owner field for each of these mappings specifies the EE which is
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* allowed to write to the APID. The owner of the last (highest) APID
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* for a given PPID will receive interrupts from the PPID.
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* which has the IRQ owner bit set for a given PPID will receive
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* interrupts from the PPID.
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*
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* In arbiter version 7, the APID numbering space is divided between
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* the primary bus (0) and secondary bus (1) such that:
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* APID = 0 to N-1 are assigned to the primary bus
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* APID = N to N+M-1 are assigned to the secondary bus
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* where N = number of APIDs supported by the primary bus and
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* M = number of APIDs supported by the secondary bus
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*/
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for (i = 0; ; i++, apidd++) {
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apidd = &pmic_arb->apid_data[pmic_arb->base_apid];
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apid_max = pmic_arb->base_apid + pmic_arb->apid_count;
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for (i = pmic_arb->base_apid; i < apid_max; i++, apidd++) {
|
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offset = pmic_arb->ver_ops->apid_map_offset(i);
|
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if (offset >= pmic_arb->core_size)
|
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break;
|
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|
|
@ -1005,8 +1101,8 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
|
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ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
|
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is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
|
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|
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regval = readl_relaxed(pmic_arb->cnfg +
|
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SPMI_OWNERSHIP_TABLE_REG(i));
|
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regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
|
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i));
|
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apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
|
||||
|
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apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
|
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|
|
@ -1015,16 +1111,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
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apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
|
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prev_apidd = &pmic_arb->apid_data[apid];
|
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|
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if (valid && is_irq_ee &&
|
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prev_apidd->write_ee == pmic_arb->ee) {
|
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if (!valid || apidd->write_ee == pmic_arb->ee) {
|
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/* First PPID mapping or one for this EE */
|
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pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
|
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} else if (valid && is_irq_ee &&
|
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prev_apidd->write_ee == pmic_arb->ee) {
|
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/*
|
||||
* Duplicate PPID mapping after the one for this EE;
|
||||
* override the irq owner
|
||||
*/
|
||||
prev_apidd->irq_ee = apidd->irq_ee;
|
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} else if (!valid || is_irq_ee) {
|
||||
/* First PPID mapping or duplicate for another EE */
|
||||
pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
|
||||
}
|
||||
|
||||
apidd->ppid = ppid;
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|
|
@ -1071,6 +1167,21 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
|
|||
return 0x1000 * pmic_arb->ee + 0x8000 * apid;
|
||||
}
|
||||
|
||||
static int pmic_arb_wr_addr_map_v2(struct spmi_pmic_arb *pmic_arb, u8 sid,
|
||||
u16 addr, struct resource *res_out)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = pmic_arb_offset_v2(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
res_out->start = pmic_arb->wr_base_phys + rc;
|
||||
res_out->end = res_out->start + 0x1000 - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* v5 offset per ee and per apid for observer channels and per apid for
|
||||
* read/write channels.
|
||||
|
|
@ -1093,6 +1204,11 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
|
|||
offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
|
||||
break;
|
||||
case PMIC_ARB_CHANNEL_RW:
|
||||
if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
|
||||
dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
|
||||
sid, addr);
|
||||
return -EPERM;
|
||||
}
|
||||
offset = 0x10000 * apid;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1100,6 +1216,70 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
|
|||
return offset;
|
||||
}
|
||||
|
||||
static int pmic_arb_wr_addr_map_v5(struct spmi_pmic_arb *pmic_arb, u8 sid,
|
||||
u16 addr, struct resource *res_out)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = pmic_arb_offset_v5(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
res_out->start = pmic_arb->wr_base_phys + rc;
|
||||
res_out->end = res_out->start + 0x10000 - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* v7 offset per ee and per apid for observer channels and per apid for
|
||||
* read/write channels.
|
||||
*/
|
||||
static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
|
||||
enum pmic_arb_channel ch_type)
|
||||
{
|
||||
u16 apid;
|
||||
int rc;
|
||||
u32 offset = 0;
|
||||
u16 ppid = (sid << 8) | (addr >> 8);
|
||||
|
||||
rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
apid = rc;
|
||||
switch (ch_type) {
|
||||
case PMIC_ARB_CHANNEL_OBS:
|
||||
offset = 0x8000 * pmic_arb->ee + 0x20 * apid;
|
||||
break;
|
||||
case PMIC_ARB_CHANNEL_RW:
|
||||
if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
|
||||
dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
|
||||
sid, addr);
|
||||
return -EPERM;
|
||||
}
|
||||
offset = 0x1000 * apid;
|
||||
break;
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
static int pmic_arb_wr_addr_map_v7(struct spmi_pmic_arb *pmic_arb, u8 sid,
|
||||
u16 addr, struct resource *res_out)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = pmic_arb_offset_v7(pmic_arb, sid, addr, PMIC_ARB_CHANNEL_RW);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
res_out->start = pmic_arb->wr_base_phys + rc;
|
||||
res_out->end = res_out->start + 0x1000 - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
|
||||
{
|
||||
return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
|
||||
|
|
@ -1134,6 +1314,12 @@ pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
|
|||
return pmic_arb->intr + 0x10000 * m + 0x4 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
|
||||
{
|
||||
return pmic_arb->intr + 0x1000 * m + 0x4 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
|
|
@ -1152,6 +1338,12 @@ pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
|
|||
return pmic_arb->wr_base + 0x100 + 0x10000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->wr_base + 0x100 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
|
|
@ -1170,6 +1362,12 @@ pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
|
|||
return pmic_arb->wr_base + 0x104 + 0x10000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->wr_base + 0x104 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
|
|
@ -1188,6 +1386,12 @@ pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
|
|||
return pmic_arb->wr_base + 0x108 + 0x10000 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->wr_base + 0x108 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v2(u16 n)
|
||||
{
|
||||
return 0x800 + 0x4 * n;
|
||||
|
|
@ -1198,6 +1402,28 @@ static u32 pmic_arb_apid_map_offset_v5(u16 n)
|
|||
return 0x900 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_apid_map_offset_v7(u16 n)
|
||||
{
|
||||
return 0x2000 + 0x4 * n;
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->cnfg + 0x700 + 0x4 * n;
|
||||
}
|
||||
|
||||
/*
|
||||
* For arbiter version 7, APID ownership table registers have independent
|
||||
* numbering space for each SPMI bus instance, so each is indexed starting from
|
||||
* 0.
|
||||
*/
|
||||
static void __iomem *
|
||||
pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
|
||||
{
|
||||
return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid);
|
||||
}
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
||||
.ver_str = "v1",
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v1,
|
||||
|
|
@ -1209,6 +1435,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
|||
.irq_status = pmic_arb_irq_status_v1,
|
||||
.irq_clear = pmic_arb_irq_clear_v1,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
.wr_addr_map = pmic_arb_wr_addr_map_v1,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
|
||||
|
|
@ -1222,6 +1449,8 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 = {
|
|||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
.apid_owner = pmic_arb_apid_owner_v2,
|
||||
.wr_addr_map = pmic_arb_wr_addr_map_v2,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v3 = {
|
||||
|
|
@ -1235,6 +1464,8 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 = {
|
|||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v2,
|
||||
.apid_owner = pmic_arb_apid_owner_v2,
|
||||
.wr_addr_map = pmic_arb_wr_addr_map_v2,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v5 = {
|
||||
|
|
@ -1248,6 +1479,23 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 = {
|
|||
.irq_status = pmic_arb_irq_status_v5,
|
||||
.irq_clear = pmic_arb_irq_clear_v5,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v5,
|
||||
.apid_owner = pmic_arb_apid_owner_v2,
|
||||
.wr_addr_map = pmic_arb_wr_addr_map_v5,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v7 = {
|
||||
.ver_str = "v7",
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v5,
|
||||
.non_data_cmd = pmic_arb_non_data_cmd_v2,
|
||||
.offset = pmic_arb_offset_v7,
|
||||
.fmt_cmd = pmic_arb_fmt_cmd_v2,
|
||||
.owner_acc_status = pmic_arb_owner_acc_status_v7,
|
||||
.acc_enable = pmic_arb_acc_enable_v7,
|
||||
.irq_status = pmic_arb_irq_status_v7,
|
||||
.irq_clear = pmic_arb_irq_clear_v7,
|
||||
.apid_map_offset = pmic_arb_apid_map_offset_v7,
|
||||
.apid_owner = pmic_arb_apid_owner_v7,
|
||||
.wr_addr_map = pmic_arb_wr_addr_map_v7,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
||||
|
|
@ -1257,6 +1505,180 @@ static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
|||
.translate = qpnpint_irq_domain_translate,
|
||||
};
|
||||
|
||||
static int _spmi_pmic_arb_map_address(struct spmi_pmic_arb *pmic_arb,
|
||||
u32 spmi_address, struct resource *res_out)
|
||||
{
|
||||
u32 sid, addr;
|
||||
|
||||
sid = (spmi_address >> 16) & 0xF;
|
||||
addr = spmi_address & 0xFFFF;
|
||||
|
||||
return pmic_arb->ver_ops->wr_addr_map(pmic_arb, sid, addr, res_out);
|
||||
}
|
||||
|
||||
/**
|
||||
* spmi_pmic_arb_map_address() - returns physical addresses of registers used to
|
||||
* write to the PMIC peripheral at spmi_address
|
||||
* @dev: Consumer device pointer
|
||||
* @spmi_address: 20-bit SPMI address of the form: 0xSPPPP
|
||||
* where S = global PMIC SID and
|
||||
* PPPP = SPMI address within the slave
|
||||
* @res_out: Resource struct (allocated by the caller) in which
|
||||
* physical addresses for the range are passed via start
|
||||
* and end elements
|
||||
*
|
||||
* Returns: 0 on success or an errno on failure.
|
||||
*/
|
||||
int spmi_pmic_arb_map_address(const struct device *dev, u32 spmi_address,
|
||||
struct resource *res_out)
|
||||
{
|
||||
struct device_node *ctrl_node;
|
||||
struct platform_device *ctrl_pdev;
|
||||
struct spmi_controller *ctrl;
|
||||
struct spmi_pmic_arb *pmic_arb;
|
||||
|
||||
if (!dev || !dev->of_node || !res_out) {
|
||||
pr_err("%s: Invalid pointer\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ctrl_node = of_parse_phandle(dev->of_node, "qcom,pmic-arb", 0);
|
||||
if (!ctrl_node) {
|
||||
pr_err("%s: Could not find PMIC arbiter node via qcom,pmic-arb property\n",
|
||||
__func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ctrl_pdev = of_find_device_by_node(ctrl_node);
|
||||
of_node_put(ctrl_node);
|
||||
if (!ctrl_pdev)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ctrl = platform_get_drvdata(ctrl_pdev);
|
||||
if (!ctrl)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
pmic_arb = spmi_controller_get_drvdata(ctrl);
|
||||
if (!pmic_arb) {
|
||||
pr_err("Missing PMIC arbiter device\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return _spmi_pmic_arb_map_address(pmic_arb, spmi_address, res_out);
|
||||
}
|
||||
EXPORT_SYMBOL(spmi_pmic_arb_map_address);
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static int debug_spmi_addr_get(void *data, u64 *val)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = data;
|
||||
|
||||
*val = pmic_arb->debug_spmi_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int debug_spmi_addr_set(void *data, u64 val)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = data;
|
||||
|
||||
pmic_arb->debug_spmi_addr = val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(debug_spmi_addr_fops, debug_spmi_addr_get,
|
||||
debug_spmi_addr_set, "0x%05llX\n");
|
||||
|
||||
static int debug_soc_start_addr_get(void *data, u64 *val)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = data;
|
||||
struct resource res = {0};
|
||||
int err;
|
||||
|
||||
err = _spmi_pmic_arb_map_address(pmic_arb, pmic_arb->debug_spmi_addr,
|
||||
&res);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
*val = res.start;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(debug_soc_start_addr_fops, debug_soc_start_addr_get,
|
||||
NULL, "0x%llX\n");
|
||||
|
||||
static int debug_soc_end_addr_get(void *data, u64 *val)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb = data;
|
||||
struct resource res = {0};
|
||||
int err;
|
||||
|
||||
err = _spmi_pmic_arb_map_address(pmic_arb, pmic_arb->debug_spmi_addr,
|
||||
&res);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
*val = res.end;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(debug_soc_end_addr_fops, debug_soc_end_addr_get,
|
||||
NULL, "0x%llX\n");
|
||||
|
||||
static void spmi_pmic_arb_debugfs_init(struct spmi_pmic_arb *pmic_arb)
|
||||
{
|
||||
struct dentry *dir, *file;
|
||||
char buf[10];
|
||||
|
||||
scnprintf(buf, sizeof(buf), "spmi%u", pmic_arb->spmic->nr);
|
||||
|
||||
dir = debugfs_create_dir(buf, NULL);
|
||||
if (IS_ERR(dir)) {
|
||||
dev_err(&pmic_arb->spmic->dev, "Could not create %s debugfs directory, rc=%ld\n",
|
||||
buf, PTR_ERR(dir));
|
||||
return;
|
||||
}
|
||||
pmic_arb->debugfs = dir;
|
||||
|
||||
dir = debugfs_create_dir("address_map", pmic_arb->debugfs);
|
||||
if (IS_ERR(dir)) {
|
||||
dev_err(&pmic_arb->spmic->dev, "Could not create address_map debugfs directory, rc=%ld\n",
|
||||
PTR_ERR(dir));
|
||||
goto error;
|
||||
}
|
||||
|
||||
file = debugfs_create_file_unsafe("spmi_addr", 0600, dir, pmic_arb,
|
||||
&debug_spmi_addr_fops);
|
||||
if (IS_ERR(file)) {
|
||||
dev_err(&pmic_arb->spmic->dev, "Could not create spmi_addr debugfs file, rc=%ld\n",
|
||||
PTR_ERR(file));
|
||||
goto error;
|
||||
}
|
||||
|
||||
file = debugfs_create_file_unsafe("soc_addr_start", 0400, dir, pmic_arb,
|
||||
&debug_soc_start_addr_fops);
|
||||
if (IS_ERR(file)) {
|
||||
dev_err(&pmic_arb->spmic->dev, "Could not create soc_addr_start debugfs file, rc=%ld\n",
|
||||
PTR_ERR(file));
|
||||
goto error;
|
||||
}
|
||||
|
||||
file = debugfs_create_file_unsafe("soc_addr_end", 0400, dir, pmic_arb,
|
||||
&debug_soc_end_addr_fops);
|
||||
if (IS_ERR(file)) {
|
||||
dev_err(&pmic_arb->spmic->dev, "Could not create soc_addr_end debugfs file, rc=%ld\n",
|
||||
PTR_ERR(file));
|
||||
goto error;
|
||||
}
|
||||
|
||||
return;
|
||||
error:
|
||||
debugfs_remove_recursive(pmic_arb->debugfs);
|
||||
}
|
||||
#else
|
||||
static void spmi_pmic_arb_debugfs_init(struct spmi_pmic_arb *pmic_arb) { }
|
||||
#endif
|
||||
|
||||
static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spmi_pmic_arb *pmic_arb;
|
||||
|
|
@ -1274,8 +1696,18 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
pmic_arb = spmi_controller_get_drvdata(ctrl);
|
||||
pmic_arb->spmic = ctrl;
|
||||
|
||||
/*
|
||||
* Please don't replace this with devm_platform_ioremap_resource() or
|
||||
* devm_ioremap_resource(). These both result in a call to
|
||||
* devm_request_mem_region() which prevents multiple mappings of this
|
||||
* register address range. SoCs with PMIC arbiter v7 may define two
|
||||
* arbiter devices, for the two physical SPMI interfaces, which share
|
||||
* some register address ranges (i.e. "core", "obsrvr", and "chnls").
|
||||
* Ensure that both devices probe successfully by calling devm_ioremap()
|
||||
* which does not result in a devm_request_mem_region() call.
|
||||
*/
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
|
||||
core = devm_ioremap_resource(&ctrl->dev, res);
|
||||
core = devm_ioremap(&ctrl->dev, res->start, resource_size(res));
|
||||
if (IS_ERR(core)) {
|
||||
err = PTR_ERR(core);
|
||||
goto err_put_ctrl;
|
||||
|
|
@ -1296,6 +1728,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
|
||||
pmic_arb->ver_ops = &pmic_arb_v1;
|
||||
pmic_arb->wr_base = core;
|
||||
pmic_arb->wr_base_phys = res->start;
|
||||
pmic_arb->rd_base = core;
|
||||
} else {
|
||||
pmic_arb->core = core;
|
||||
|
|
@ -1304,12 +1737,15 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
pmic_arb->ver_ops = &pmic_arb_v2;
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v3;
|
||||
else
|
||||
else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)
|
||||
pmic_arb->ver_ops = &pmic_arb_v5;
|
||||
else
|
||||
pmic_arb->ver_ops = &pmic_arb_v7;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"obsrvr");
|
||||
pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
pmic_arb->rd_base = devm_ioremap(&ctrl->dev, res->start,
|
||||
resource_size(res));
|
||||
if (IS_ERR(pmic_arb->rd_base)) {
|
||||
err = PTR_ERR(pmic_arb->rd_base);
|
||||
goto err_put_ctrl;
|
||||
|
|
@ -1317,11 +1753,69 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"chnls");
|
||||
pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
pmic_arb->wr_base = devm_ioremap(&ctrl->dev, res->start,
|
||||
resource_size(res));
|
||||
if (IS_ERR(pmic_arb->wr_base)) {
|
||||
err = PTR_ERR(pmic_arb->wr_base);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
pmic_arb->wr_base_phys = res->start;
|
||||
}
|
||||
|
||||
pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
|
||||
|
||||
if (hw_ver >= PMIC_ARB_VERSION_V7_MIN) {
|
||||
pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
|
||||
/* Optional property for v7: */
|
||||
of_property_read_u32(pdev->dev.of_node, "qcom,bus-id",
|
||||
&pmic_arb->bus_instance);
|
||||
if (pmic_arb->bus_instance > 1) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "invalid bus instance (%u) specified\n",
|
||||
pmic_arb->bus_instance);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
if (pmic_arb->bus_instance == 0) {
|
||||
pmic_arb->base_apid = 0;
|
||||
pmic_arb->apid_count =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
} else {
|
||||
pmic_arb->base_apid =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
pmic_arb->apid_count =
|
||||
readl_relaxed(core + PMIC_ARB_FEATURES1) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
}
|
||||
|
||||
if (pmic_arb->base_apid + pmic_arb->apid_count >
|
||||
pmic_arb->max_periphs) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
|
||||
pmic_arb->base_apid + pmic_arb->apid_count);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
} else if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
|
||||
pmic_arb->base_apid = 0;
|
||||
pmic_arb->apid_count = readl_relaxed(core + PMIC_ARB_FEATURES) &
|
||||
PMIC_ARB_FEATURES_PERIPH_MASK;
|
||||
|
||||
if (pmic_arb->apid_count > pmic_arb->max_periphs) {
|
||||
err = -EINVAL;
|
||||
dev_err(&pdev->dev, "Unsupported APID count %d detected\n",
|
||||
pmic_arb->apid_count);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
}
|
||||
|
||||
pmic_arb->apid_data = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
|
||||
sizeof(*pmic_arb->apid_data),
|
||||
GFP_KERNEL);
|
||||
if (!pmic_arb->apid_data) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
|
||||
|
|
@ -1341,10 +1835,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
|
||||
if (pmic_arb->irq < 0) {
|
||||
err = pmic_arb->irq;
|
||||
goto err_put_ctrl;
|
||||
if (of_find_property(pdev->dev.of_node, "interrupt-names", NULL)) {
|
||||
pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
|
||||
if (pmic_arb->irq < 0) {
|
||||
err = pmic_arb->irq;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
}
|
||||
|
||||
err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
|
||||
|
|
@ -1386,7 +1882,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
/* Initialize max_apid/min_apid to the opposite bounds, during
|
||||
* the irq domain translation, we are sure to update these */
|
||||
pmic_arb->max_apid = 0;
|
||||
pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
|
||||
pmic_arb->min_apid = pmic_arb->max_periphs - 1;
|
||||
|
||||
platform_set_drvdata(pdev, ctrl);
|
||||
raw_spin_lock_init(&pmic_arb->lock);
|
||||
|
|
@ -1404,26 +1900,35 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "adding irq domain\n");
|
||||
pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
|
||||
&pmic_arb_irq_domain_ops, pmic_arb);
|
||||
if (!pmic_arb->domain) {
|
||||
dev_err(&pdev->dev, "unable to create irq_domain\n");
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
if (pmic_arb->irq > 0) {
|
||||
dev_dbg(&pdev->dev, "adding irq domain\n");
|
||||
pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
|
||||
&pmic_arb_irq_domain_ops, pmic_arb);
|
||||
if (!pmic_arb->domain) {
|
||||
dev_err(&pdev->dev, "unable to create irq_domain\n");
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq,
|
||||
pmic_arb_chained_irq, pmic_arb);
|
||||
} else {
|
||||
dev_dbg(&pdev->dev, "not supporting PMIC interrupts\n");
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
|
||||
pmic_arb);
|
||||
err = spmi_controller_add(ctrl);
|
||||
if (err)
|
||||
goto err_domain_remove;
|
||||
|
||||
spmi_pmic_arb_debugfs_init(pmic_arb);
|
||||
|
||||
return 0;
|
||||
|
||||
err_domain_remove:
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
|
||||
irq_domain_remove(pmic_arb->domain);
|
||||
if (pmic_arb->irq > 0) {
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
|
||||
irq_domain_remove(pmic_arb->domain);
|
||||
}
|
||||
err_put_ctrl:
|
||||
spmi_controller_put(ctrl);
|
||||
return err;
|
||||
|
|
@ -1433,9 +1938,12 @@ static int spmi_pmic_arb_remove(struct platform_device *pdev)
|
|||
{
|
||||
struct spmi_controller *ctrl = platform_get_drvdata(pdev);
|
||||
struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
|
||||
debugfs_remove_recursive(pmic_arb->debugfs);
|
||||
spmi_controller_remove(ctrl);
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
|
||||
irq_domain_remove(pmic_arb->domain);
|
||||
if (pmic_arb->irq > 0) {
|
||||
irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
|
||||
irq_domain_remove(pmic_arb->domain);
|
||||
}
|
||||
spmi_controller_put(ctrl);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1452,9 +1960,21 @@ static struct platform_driver spmi_pmic_arb_driver = {
|
|||
.driver = {
|
||||
.name = "spmi_pmic_arb",
|
||||
.of_match_table = spmi_pmic_arb_match_table,
|
||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||||
},
|
||||
};
|
||||
module_platform_driver(spmi_pmic_arb_driver);
|
||||
|
||||
static int __init spmi_pmic_arb_init(void)
|
||||
{
|
||||
return platform_driver_register(&spmi_pmic_arb_driver);
|
||||
}
|
||||
arch_initcall(spmi_pmic_arb_init);
|
||||
|
||||
static void __exit spmi_pmic_arb_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&spmi_pmic_arb_driver);
|
||||
}
|
||||
module_exit(spmi_pmic_arb_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:spmi_pmic_arb");
|
||||
|
|
|
|||
22
include/linux/soc/qcom/spmi-pmic-arb.h
Normal file
22
include/linux/soc/qcom/spmi-pmic-arb.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
|
||||
|
||||
#ifndef _SPMI_PMIC_ARB_H
|
||||
#define _SPMI_PMIC_ARB_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#if IS_ENABLED(CONFIG_SPMI_MSM_PMIC_ARB)
|
||||
int spmi_pmic_arb_map_address(const struct device *dev, u32 spmi_address,
|
||||
struct resource *res_out);
|
||||
#else
|
||||
static inline int spmi_pmic_arb_map_address(const struct device *dev,
|
||||
u32 spmi_address, struct resource *res_out)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user