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arm64: dts: mediatek: add mmc support for mt8365-evk

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- Add EMMC support on mmc0 (internal memory)
- Add SD-UHS support on mmc1 (external memory)

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-5-7019f3fd0adf@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Alexandre Mergnat 2023-05-25 10:33:14 +02:00 committed by Matthias Brugger
parent 56e9f0f4aa
commit 6e8270afad
1 changed files with 138 additions and 0 deletions
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138
arch/arm64/boot/dts/mediatek/mt8365-evk.dts
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@ -95,6 +95,42 @@ &i2c0 {
status = "okay";
};
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
hs400-ds-delay = <0x12012>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sd;
no-sdio;
non-removable;
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&mt6357_vemc_reg>;
vqmmc-supply = <&mt6357_vio18_reg>;
status = "okay";
};
&mmc1 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
max-frequency = <200000000>;
pinctrl-0 = <&mmc1_default_pins>;
pinctrl-1 = <&mmc1_uhs_pins>;
pinctrl-names = "default", "state_uhs";
sd-uhs-sdr104;
sd-uhs-sdr50;
vmmc-supply = <&mt6357_vmch_reg>;
vqmmc-supply = <&mt6357_vmc_reg>;
status = "okay";
};
&mt6357_pmic {
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
@ -118,6 +154,108 @@ pins {
};
};
mmc0_default_pins: mmc0-default-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
bias-pull-down;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up;
};
rst-pins {
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
ds-pins {
pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
rst-pins {
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-up;
};
};
mmc1_default_pins: mmc1-default-pins {
cd-pins {
pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
bias-pull-up;
};
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc1_uhs_pins: mmc1-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
cmd-dat-pins {
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
uart0_pins: uart0-pins {
pins {
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,