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Scheduler fixes:

Browse Source 
- Fix MM CID affinity-triggered switch back to per-task mode
    (Hui Su)
 
  - Fix scheduling regression observed on AMD Ryzen
    AI HX 370 systems, caused by cache aware scheduling
    incorrectly overriding asym packing placement (Tim Chen)
 
  - Fix stale get_pref_llc() prototype for !CONFIG_SCHED_CACHE
    (Yafang Shao)
 
 Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Merge tag 'sched-urgent-2026-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull scheduler fixes from Ingo Molnar:

 - Fix MM CID affinity-triggered switch back to per-task mode
   (Hui Su)

 - Fix scheduling regression observed on AMD Ryzen
   AI HX 370 systems, caused by cache aware scheduling
   incorrectly overriding asym packing placement (Tim Chen)

 - Fix stale get_pref_llc() prototype for !CONFIG_SCHED_CACHE
   (Yafang Shao)

* tag 'sched-urgent-2026-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  sched: fix stale get_pref_llc() stub for !CONFIG_SCHED_CACHE
  sched/cache: Honor asym packing over cache aware scheduling on hybrid systems
  sched/mmcid: Fix affinity-triggered switch back to per-task mode
This commit is contained in:
Linus Torvalds 2026-10-25 17:53:13 -10:00
commit 6e723c4f94
2 changed files with 20 additions and 7 deletions
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5
kernel/sched/core.c
View File

@ -10783,11 +10783,10 @@ static void __mm_update_max_cids(struct mm_mm_cid *mc)
static inline unsigned int mm_cid_calc_pcpu_thrs(struct mm_mm_cid *mc)
{
unsigned int opt_cids;
unsigned int nr_cpus = mc->nr_cpus_allowed;
opt_cids = min(mc->nr_cpus_allowed, mc->users);
/* Has to be at least 1 because 0 indicates PCPU mode off */
return max(min(opt_cids - opt_cids / 4, num_possible_cpus() / 2), 1);
return max(min(nr_cpus - nr_cpus / 4, num_possible_cpus() / 2), 1);
}
static bool mm_update_max_cids(struct mm_struct *mm)

22
kernel/sched/fair.c
View File

@ -2138,7 +2138,7 @@ void init_sched_mm(struct task_struct *p) { }
static void task_tick_cache(struct rq *rq, struct task_struct *p) { }
static inline int get_pref_llc(struct task_struct *p,
struct mm_struct *mm)
struct sched_cache_group *grp)
{
return -1;
}
@ -10940,6 +10940,8 @@ static inline bool task_misfits_asym_cpu(struct lb_env *env, struct task_struct
return false;
}
static inline bool sched_asym(struct sched_domain *sd, int dst_cpu, int src_cpu);
/*
* Check if task p can migrate from source LLC to
* destination LLC in terms of cache aware load balance.
@ -10964,6 +10966,10 @@ static enum llc_mig can_migrate_llc_task(struct lb_env *env,
if (cpu < 0 || cpus_share_cache(src_cpu, dst_cpu))
return mig_unrestricted;
/* Prioritize asym packing to idle core over cache awareness */
if (env->idle && sched_asym(env->sd, dst_cpu, src_cpu))
return mig_unrestricted;
/* skip cache aware load balance for too many threads */
if (invalid_llc_nr(grp, p, dst_cpu) ||
exceed_llc_capacity(grp, dst_cpu)) {
@ -12154,6 +12160,14 @@ static inline bool llc_balance(struct lb_env *env, struct sg_lb_stats *sgs,
sgs->group_misfit_task_load)
return false;
/*
* On asym packing domains, if the destination CPU
* has higher priority than all CPUs in the source group,
* prioritize asym packing.
*/
if (sgs->group_asym_packing)
return false;
/*
* Skip cache aware tagging if nr_balanced_failed is sufficiently high.
* Threshold of cache_nice_tries is set to 1 higher than nr_balance_failed
@ -13569,12 +13583,12 @@ static int need_active_balance(struct lb_env *env)
{
struct sched_domain *sd = env->sd;
if (alb_break_llc(env))
return 0;
if (asym_active_balance(env))
return 1;
if (alb_break_llc(env))
return 0;
if (imbalanced_active_balance(env))
return 1;