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drm/amd/display: Add DML support for dcn42
DML support for DCN 4.2 Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li
Alex Deucher
parent
5b880e37a8
commit
6e5b72ac22
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@ -90,6 +90,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags)
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@ -107,6 +108,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(d
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags)
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@ -124,6 +126,7 @@ DML21 += src/dml2_core/dml2_core_dcn4_calcs.o
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DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o
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DML21 += src/dml2_dpmm/dml2_dpmm_factory.o
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DML21 += src/dml2_mcg/dml2_mcg_dcn4.o
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DML21 += src/dml2_mcg/dml2_mcg_dcn42.o
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DML21 += src/dml2_mcg/dml2_mcg_factory.o
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DML21 += src/dml2_pmo/dml2_pmo_dcn3.o
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DML21 += src/dml2_pmo/dml2_pmo_factory.o
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@ -45,6 +45,9 @@ static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_versi
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case DCN_VERSION_4_01:
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project_id = dml2_project_dcn4x_stage2_auto_drr_svp;
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break;
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case DCN_VERSION_4_2:
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project_id = dml2_project_dcn42;
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break;
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default:
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project_id = dml2_project_invalid;
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DC_ERR("unsupported dcn version for DML21!");
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@ -615,6 +618,13 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
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case DC_CM2_GPU_MEM_SIZE_171717:
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plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube;
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break;
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case DC_CM2_GPU_MEM_SIZE_333333:
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plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube;
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break;
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// handling when use case and HW support available
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case DC_CM2_GPU_MEM_SIZE_454545:
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case DC_CM2_GPU_MEM_SIZE_656565:
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break;
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case DC_CM2_GPU_MEM_SIZE_TRANSFORMED:
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default:
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//plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined
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@ -824,6 +834,9 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
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context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;
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context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
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context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
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context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
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context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;
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context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/
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}
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static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)
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@ -19,6 +19,7 @@ enum dml2_project_id {
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dml2_project_dcn4x_stage1,
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dml2_project_dcn4x_stage2,
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dml2_project_dcn4x_stage2_auto_drr_svp,
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dml2_project_dcn42,
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};
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enum dml2_pstate_change_support {
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@ -78,6 +78,86 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = {
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.subvp_swath_height_margin_lines = 16,
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};
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struct dml2_core_ip_params core_dcn42_ip_caps_base = {
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.vblank_nom_default_us = 668,
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.remote_iommu_outstanding_translations = 256,
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.rob_buffer_size_kbytes = 64,
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.config_return_buffer_size_in_kbytes = 1792,
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.config_return_buffer_segment_size_in_kbytes = 64,
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.compressed_buffer_segment_size_in_kbytes = 64,
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.dpte_buffer_size_in_pte_reqs_luma = 68,
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.dpte_buffer_size_in_pte_reqs_chroma = 36,
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.pixel_chunk_size_kbytes = 8,
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.alpha_pixel_chunk_size_kbytes = 4,
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.min_pixel_chunk_size_bytes = 1024,
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.writeback_chunk_size_kbytes = 8,
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.line_buffer_size_bits = 1171920,
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.max_line_buffer_lines = 32,
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.writeback_interface_buffer_size_kbytes = 90,
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//Number of pipes after DCN Pipe harvesting
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.max_num_dpp = 4,
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.max_num_otg = 4,
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.max_num_opp = 4,
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.max_num_wb = 1,
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.max_dchub_pscl_bw_pix_per_clk = 4,
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.max_pscl_lb_bw_pix_per_clk = 2,
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.max_lb_vscl_bw_pix_per_clk = 4,
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.max_vscl_hscl_bw_pix_per_clk = 4,
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.max_hscl_ratio = 6,
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.max_vscl_ratio = 6,
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.max_hscl_taps = 8,
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.max_vscl_taps = 8,
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.dispclk_ramp_margin_percent = 1,
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.dppclk_delay_subtotal = 47,
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.dppclk_delay_scl = 50,
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.dppclk_delay_scl_lb_only = 16,
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.dppclk_delay_cnvc_formatter = 28,
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.dppclk_delay_cnvc_cursor = 6,
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.cursor_buffer_size = 42,
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.cursor_chunk_size = 2,
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.dispclk_delay_subtotal = 125,
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.max_inter_dcn_tile_repeaters = 8,
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.writeback_max_hscl_ratio = 1,
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.writeback_max_vscl_ratio = 1,
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.writeback_min_hscl_ratio = 1,
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.writeback_min_vscl_ratio = 1,
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.writeback_max_hscl_taps = 1,
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.writeback_max_vscl_taps = 1,
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.writeback_line_buffer_buffer_size = 0,
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.num_dsc = 4,
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.maximum_dsc_bits_per_component = 12,
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.maximum_pixels_per_line_per_dsc_unit = 5760,
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.dsc422_native_support = true,
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.dcc_supported = true,
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.ptoi_supported = false,
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.cursor_64bpp_support = true,
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.dynamic_metadata_vm_enabled = false,
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.max_num_hdmi_frl_outputs = 0,
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.max_num_dp2p0_outputs = 2,
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.max_num_dp2p0_streams = 4,
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.imall_supported = 1,
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.max_flip_time_us = 110,
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.max_flip_time_lines = 50,
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.words_per_channel = 16,
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.subvp_fw_processing_delay_us = 15,
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.subvp_pstate_allow_width_us = 20,
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.subvp_swath_height_margin_lines = 16,
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.dcn_mrq_present = 1,
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.zero_size_buffer_entries = 512,
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.compbuf_reserved_space_zs = 64,
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.dcc_meta_buffer_size_bytes = 6272,
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.meta_chunk_size_kbytes = 2,
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.min_meta_chunk_size_bytes = 256,
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.dchub_arb_to_ret_delay = 102,
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.hostvm_mode = 1,
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};
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static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params)
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{
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ip_caps->pipe_count = ip_params->max_num_dpp;
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@ -153,6 +233,37 @@ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out)
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return true;
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}
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bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out)
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{
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struct dml2_core_instance *core = in_out->instance;
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if (!in_out->minimum_clock_table)
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return false;
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else
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core->minimum_clock_table = in_out->minimum_clock_table;
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if (in_out->explicit_ip_bb && in_out->explicit_ip_bb_size > 0) {
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memcpy(&core->clean_me_up.mode_lib.ip, in_out->explicit_ip_bb, in_out->explicit_ip_bb_size);
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// FIXME_STAGE2:
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// DV still uses stage1 ip_param_st for each variant, need to patch the ip_caps with ip_param info
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// Should move DV to use ip_caps but need move more overrides to ip_caps
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patch_ip_caps_with_explicit_ip_params(in_out->ip_caps, in_out->explicit_ip_bb);
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core->clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;
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core->clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;
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core->clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines;
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} else {
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memcpy(&core->clean_me_up.mode_lib.ip, &core_dcn42_ip_caps_base, sizeof(struct dml2_core_ip_params));
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patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps);
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core->clean_me_up.mode_lib.ip.imall_supported = false;
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}
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memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb));
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memcpy(&core->clean_me_up.mode_lib.ip_caps, in_out->ip_caps, sizeof(struct dml2_ip_capabilities));
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return true;
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}
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static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,
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const struct dml2_implicit_svp_meta *meta)
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{
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@ -5,6 +5,7 @@
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#ifndef __DML2_CORE_DCN4_H__
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#define __DML2_CORE_DCN4_H__
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bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out);
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bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out);
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bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out);
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bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out);
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bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out);
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@ -30,6 +30,14 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance
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out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation;
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result = true;
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break;
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case dml2_project_dcn42:
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out->initialize = &core_dcn42_initialize;
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out->mode_support = &core_dcn4_mode_support;
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out->mode_programming = &core_dcn4_mode_programming;
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out->populate_informative = &core_dcn4_populate_informative;
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out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation;
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result = true;
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break;
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case dml2_project_invalid:
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default:
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break;
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@ -802,3 +802,37 @@ bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_
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return true;
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}
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bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out)
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{
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const struct dml2_display_cfg *display_cfg = &in_out->display_cfg->display_config;
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const struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->core->clean_me_up.mode_lib;
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struct dml2_dchub_global_register_set *dchubbub_regs = &in_out->programming->global_regs;
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double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz;
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/* set A */
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter = (int unsigned)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit = (int unsigned)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].temp_read_or_ppt = (int unsigned)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].urgent = (int unsigned)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].usr = (int unsigned)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_flip = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthImmediateFlip * 1000);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_nom = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidth * 1000);
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_mall = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthMALL * 1000);
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/* set B */
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A];
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_C] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A];
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dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_D] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A];
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dchubbub_regs->num_watermark_sets = 4;
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return true;
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}
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@ -10,5 +10,6 @@
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bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);
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bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);
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bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out);
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bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -41,6 +41,11 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance
|
|||
out->map_watermarks = &dpmm_dcn4_map_watermarks;
|
||||
result = true;
|
||||
break;
|
||||
case dml2_project_dcn42:
|
||||
out->map_mode_to_soc_dpm = &dpmm_dcn4_map_mode_to_soc_dpm;
|
||||
out->map_watermarks = &dpmm_dcn42_map_watermarks;
|
||||
result = true;
|
||||
break;
|
||||
case dml2_project_invalid:
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,76 @@
|
|||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright 2026 Advanced Micro Devices, Inc.
|
||||
|
||||
#include "dml2_mcg_dcn42.h"
|
||||
#include "dml_top_soc_parameter_types.h"
|
||||
|
||||
static unsigned long long uclk_to_dram_bw_kbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, unsigned long wck_ratio)
|
||||
{
|
||||
unsigned long long bw_kbps = 0;
|
||||
|
||||
bw_kbps = (unsigned long long) uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * wck_ratio * 2;
|
||||
return bw_kbps;
|
||||
}
|
||||
|
||||
static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < soc_bb->clk_table.fclk.num_clk_values; i++) {
|
||||
if (i < soc_bb->clk_table.uclk.num_clk_values) {
|
||||
min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps =
|
||||
uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config, soc_bb->clk_table.wck_ratio.clk_values_khz[i]);
|
||||
min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[i];
|
||||
} else {
|
||||
min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = min_table->dram_bw_table.entries[soc_bb->clk_table.uclk.num_clk_values - 1].pre_derate_dram_bw_kbps;
|
||||
min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[soc_bb->clk_table.uclk.num_clk_values - 1];
|
||||
}
|
||||
|
||||
min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i];
|
||||
min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i];
|
||||
}
|
||||
min_table->dram_bw_table.num_entries = soc_bb->clk_table.fclk.num_clk_values;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
|
||||
{
|
||||
bool result;
|
||||
|
||||
if (!soc_bb || !min_table)
|
||||
return false;
|
||||
|
||||
|
||||
if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE)
|
||||
return false;
|
||||
|
||||
min_table->fixed_clocks_khz.amclk = 0;
|
||||
min_table->fixed_clocks_khz.dprefclk = soc_bb->dprefclk_mhz * 1000;
|
||||
min_table->fixed_clocks_khz.pcierefclk = soc_bb->pcie_refclk_mhz * 1000;
|
||||
min_table->fixed_clocks_khz.dchubrefclk = soc_bb->dchub_refclk_mhz * 1000;
|
||||
min_table->fixed_clocks_khz.xtalclk = soc_bb->xtalclk_mhz * 1000;
|
||||
|
||||
min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dispclk.num_clk_values - 1];
|
||||
min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppclk.num_clk_values - 1];
|
||||
min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dscclk.num_clk_values - 1];
|
||||
min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1];
|
||||
min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values - 1];
|
||||
|
||||
min_table->max_ss_clocks_khz.dispclk = (unsigned int)((double)min_table->max_clocks_khz.dispclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0));
|
||||
min_table->max_ss_clocks_khz.dppclk = (unsigned int)((double)min_table->max_clocks_khz.dppclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0));
|
||||
min_table->max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table->max_clocks_khz.dtbclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0));
|
||||
|
||||
min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values - 1];
|
||||
min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values - 1];
|
||||
|
||||
result = build_min_clk_table_coarse_grained(soc_bb, min_table);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)
|
||||
{
|
||||
return build_min_clock_table(in_out->soc_bb, in_out->min_clk_table);
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
/* Copyright 2026 Advanced Micro Devices, Inc. */
|
||||
|
||||
#ifndef __DML2_MCG_DCN42_H__
|
||||
#define __DML2_MCG_DCN42_H__
|
||||
|
||||
#include "dml2_internal_shared_types.h"
|
||||
|
||||
bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);
|
||||
|
||||
#endif
|
||||
|
|
@ -4,6 +4,7 @@
|
|||
|
||||
#include "dml2_mcg_factory.h"
|
||||
#include "dml2_mcg_dcn4.h"
|
||||
#include "dml2_mcg_dcn42.h"
|
||||
#include "dml2_external_lib_deps.h"
|
||||
|
||||
static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)
|
||||
|
|
@ -30,6 +31,10 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *
|
|||
out->build_min_clock_table = &mcg_dcn4_build_min_clock_table;
|
||||
result = true;
|
||||
break;
|
||||
case dml2_project_dcn42:
|
||||
out->build_min_clock_table = &mcg_dcn42_build_min_clock_table;
|
||||
result = true;
|
||||
break;
|
||||
case dml2_project_invalid:
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
|
|||
case dml2_project_dcn4x_stage1:
|
||||
case dml2_project_dcn4x_stage2:
|
||||
case dml2_project_dcn4x_stage2_auto_drr_svp:
|
||||
case dml2_project_dcn42:
|
||||
return dml2_top_soc15_initialize_instance(in_out);
|
||||
case dml2_project_invalid:
|
||||
default:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user