drm/i915/lt_phy: Add lane_count to PLL state

Cache lane count as part of PLL state.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-6-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2026-03-12 08:06:38 +00:00
parent f52bbb00de
commit 6e1c3b80ee
2 changed files with 6 additions and 4 deletions

View File

@ -278,6 +278,7 @@ struct intel_lt_phy_pll_state {
u8 config[3];
bool ssc_enabled;
bool tbt_mode;
int lane_count;
};
struct intel_dpll_hw_state {

View File

@ -1767,11 +1767,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
}
crtc_state->dpll_hw_state.ltpll.ssc_enabled =
intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
return 0;
}
}
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
crtc_state->port_clock);
}
@ -1811,11 +1813,11 @@ intel_lt_phy_program_pll(struct intel_encoder *encoder,
static void
intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
const struct intel_lt_phy_pll_state *ltpll,
u8 lane_count)
const struct intel_lt_phy_pll_state *ltpll)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->lane_reversal;
u8 lane_count = ltpll->lane_count;
bool is_dp_alt =
intel_tc_port_in_dp_alt_mode(dig_port);
enum intel_tc_pin_assignment tc_pin =
@ -2025,8 +2027,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
XELPDP_P0_STATE_ACTIVE);
intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
crtc_state->lane_count);
intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
intel_lt_phy_transaction_end(encoder, wakeref);
}