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drm/i915/lt_phy: Add lane_count to PLL state
Cache lane count as part of PLL state. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-6-mika.kahola@intel.com
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@ -278,6 +278,7 @@ struct intel_lt_phy_pll_state {
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u8 config[3];
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bool ssc_enabled;
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bool tbt_mode;
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int lane_count;
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};
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struct intel_dpll_hw_state {
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@ -1767,11 +1767,13 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
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}
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crtc_state->dpll_hw_state.ltpll.ssc_enabled =
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intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
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crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
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return 0;
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}
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}
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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crtc_state->dpll_hw_state.ltpll.lane_count = crtc_state->lane_count;
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return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
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crtc_state->port_clock);
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}
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@ -1811,11 +1813,11 @@ intel_lt_phy_program_pll(struct intel_encoder *encoder,
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static void
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intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
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const struct intel_lt_phy_pll_state *ltpll,
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u8 lane_count)
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const struct intel_lt_phy_pll_state *ltpll)
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{
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struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
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bool lane_reversal = dig_port->lane_reversal;
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u8 lane_count = ltpll->lane_count;
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bool is_dp_alt =
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intel_tc_port_in_dp_alt_mode(dig_port);
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enum intel_tc_pin_assignment tc_pin =
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@ -2025,8 +2027,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
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intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
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XELPDP_P0_STATE_ACTIVE);
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intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll,
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crtc_state->lane_count);
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intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
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intel_lt_phy_transaction_end(encoder, wakeref);
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}
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